CH421185A - Logisches Netzwerk zur Verarbeitung zweiphasiger Inkrementsignalfolgen - Google Patents

Logisches Netzwerk zur Verarbeitung zweiphasiger Inkrementsignalfolgen

Info

Publication number
CH421185A
CH421185A CH1041763A CH1041763A CH421185A CH 421185 A CH421185 A CH 421185A CH 1041763 A CH1041763 A CH 1041763A CH 1041763 A CH1041763 A CH 1041763A CH 421185 A CH421185 A CH 421185A
Authority
CH
Switzerland
Prior art keywords
processing
signal sequences
logical network
incremental signal
phase incremental
Prior art date
Application number
CH1041763A
Other languages
English (en)
Inventor
Lattmann Max Ing Dr
Stutz Theo Dipl-El Dr Ing
Original Assignee
Contraves Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to NL292259D priority Critical patent/NL292259A/xx
Priority to BE631718D priority patent/BE631718A/xx
Priority to NL124051D priority patent/NL124051C/xx
Priority to GB16138/63A priority patent/GB1005054A/en
Priority to FR933390A priority patent/FR1360026A/fr
Application filed by Contraves Ag filed Critical Contraves Ag
Priority to CH1041763A priority patent/CH421185A/de
Priority to GB5023/64A priority patent/GB1029011A/en
Priority to DEC33411A priority patent/DE1206179B/de
Priority to NL6408340A priority patent/NL6408340A/xx
Priority to FR985093A priority patent/FR1404247A/fr
Priority to SE10080/64A priority patent/SE316034B/xx
Priority to US392998A priority patent/US3408484A/en
Priority to DEC37260A priority patent/DE1263085B/de
Priority to GB48364/65A priority patent/GB1094389A/en
Priority to NL6515016A priority patent/NL6515016A/xx
Priority to SE15366/65A priority patent/SE330039B/xx
Priority to FR46897A priority patent/FR1519525A/fr
Priority to BE676183D priority patent/BE676183A/xx
Priority to CH1255966A priority patent/CH441438A/de
Publication of CH421185A publication Critical patent/CH421185A/de
Priority to GB38620/67A priority patent/GB1198144A/en
Priority to SE11777/67A priority patent/SE339244B/xx
Priority to DEC43212A priority patent/DE1280311B/de
Priority to US856225*A priority patent/US3577085A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Optimization (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
CH1041763A 1962-05-04 1963-08-23 Logisches Netzwerk zur Verarbeitung zweiphasiger Inkrementsignalfolgen CH421185A (de)

Priority Applications (23)

Application Number Priority Date Filing Date Title
NL292259D NL292259A (de) 1962-05-04
BE631718D BE631718A (de) 1962-05-04
NL124051D NL124051C (de) 1962-05-04
GB16138/63A GB1005054A (en) 1962-05-04 1963-04-24 Improvements in and relating to electric counting arrangements
FR933390A FR1360026A (fr) 1962-05-04 1963-05-02 Système de comptage pour signaux ayant des caractéristiques déterminées
CH1041763A CH421185A (de) 1963-08-23 1963-08-23 Logisches Netzwerk zur Verarbeitung zweiphasiger Inkrementsignalfolgen
GB5023/64A GB1029011A (en) 1962-05-04 1964-02-06 Improvements in and relating to increment adding means
DEC33411A DE1206179B (de) 1962-05-04 1964-07-15 Inkrementaddierwerk
NL6408340A NL6408340A (de) 1962-05-04 1964-07-21
FR985093A FR1404247A (fr) 1962-05-04 1964-08-13 Additionneur d'accroissements
SE10080/64A SE316034B (de) 1962-05-04 1964-08-21
US392998A US3408484A (en) 1962-05-04 1964-08-24 Arrangement for counting signals of specific significance
DEC37260A DE1263085B (de) 1962-05-04 1965-10-27 Vorwaerts-Rueckwaerts-Zaehlwerk fuer zweiphasige Binaersignalfolgen mit gleichstromgekoppelten Untersetzerstufen
GB48364/65A GB1094389A (en) 1962-05-04 1965-11-15 Improvements in and relating to reversible counting mechanisms for two-phase series of binary signals
NL6515016A NL6515016A (de) 1962-05-04 1965-11-18
SE15366/65A SE330039B (de) 1962-05-04 1965-11-29
FR46897A FR1519525A (fr) 1962-05-04 1966-01-22 Compteur progressif et rétrograde de signaux binaires et biphasés
BE676183D BE676183A (de) 1962-05-04 1966-02-08
CH1255966A CH441438A (de) 1962-05-04 1966-08-30 Vorwärts-Rückwärts-Zählwerk
GB38620/67A GB1198144A (en) 1962-05-04 1967-08-22 Improvements in and relating to Reversible Counting Mechanisms
SE11777/67A SE339244B (de) 1962-05-04 1967-08-23
DEC43212A DE1280311B (de) 1962-05-04 1967-08-29 Vorwaerts-Rueckwaerts-Zaehlwerk fuer zweiphasige elektronische Binaersignalimpulsfolgen
US856225*A US3577085A (en) 1962-05-04 1969-01-09 Quinary reduction stage and forward-reverse counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1041763A CH421185A (de) 1963-08-23 1963-08-23 Logisches Netzwerk zur Verarbeitung zweiphasiger Inkrementsignalfolgen

Publications (1)

Publication Number Publication Date
CH421185A true CH421185A (de) 1966-09-30

Family

ID=4363002

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1041763A CH421185A (de) 1962-05-04 1963-08-23 Logisches Netzwerk zur Verarbeitung zweiphasiger Inkrementsignalfolgen

Country Status (1)

Country Link
CH (1) CH421185A (de)

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