US3577085A

US3577085A - Quinary reduction stage and forward-reverse counter

Info

Publication number: US3577085A
Application number: US856225*A
Authority: US
Inventors: Theo Stutz
Original assignee: Individual
Current assignee: Individual
Priority date: 1962-05-04
Filing date: 1969-01-09
Publication date: 1971-05-04
Anticipated expiration: 1988-05-04
Also published as: GB1029011A; NL124051C; DE1206179B; SE330039B; BE631718A; DE1263085B; CH441438A; SE316034B; BE676183A; FR1519525A; GB1005054A; DE1280311B; GB1198144A; SE339244B; NL292259A; US3408484A; NL6515016A; GB1094389A

Abstract

Two forms of a quinary reduction stage, for reducing the frequency of an input multiphase binary signal by a factor of five are illustrated. One corresponds to the use of a substantially minimum number of elements, while the other corresponds to use of identical binary circuits, all having the same number of inputs. By counting quarter periods of the input signal and half periods of the output signal, a decade reduction stage results. Further, each quinary reduction stage may be connected with a binary reduction stage thus furnishing a decade reduction stage, which may interconnect with other similar ones to constitute a decade forward-reverse counter.

Description

Inventor Theo Stutz Geerlisbergstrasse, 8303 Bassersdorf, Switrerland Appl. No. 856,225

Filed Jan. 9, 1969 Patented May 4, 1971 Priority May 4, 1962, Aug. 23, 1963, Apr. 7, 1965,

Aug. 3, 1966 Switzerland 5370/62, 10417/63, 4849/65 and 12559/66 Continuation-impart of application Ser. No. 679,966, Aug. 24, 1964, now abandoned Continuation-impart of application Ser. No. 538,663, Aug. 24, 1964, now abandoned Continuation-impart of application Ser. No. 392,998, Aug. 24, 1964, now abandoned Continuation-impart oi application Ser. No. 279,039, May 6, 1963, now abandoned.

QUINARY REDUCTION STAGE AND FORWARD- REVERSE COUNTER 14 Claims, 6 Drawing Figs.

[52] US. Cl 328/42, 328/44, 328/45, 328/46, 328/48 [51] Int. Cl H03k 21/00 [50] Field ofSearch 328/41, 42, 43, 44, 46, 4s

[56] References Cited UNITED STATES PATENTS 3,343,095 9/ 1 967 Offereins 328/48 3,370,237 2/1968 Reiser 328/41 Primary ExaminerJohn S. l-ieyman Attomey-Michael S. Striker ABSTRACT: Two forms of a quinary reduction stage, for reducing the frequency of an input multiphase binary signal by a factor of five are illustrated. One corresponds to the use of a substantially minimum number of elements, while the other corresponds to use of identical binary circuits, all having the same number of inputs. By counting quarter periods of the input signal and half periods of the output signal, a decade reduction stage results. Further, each quinary reduction stage may be connected with a binary reduction stage thus furnishing a decade reduction stage, which may interconnect with other similar ones to constitute a decade forward-reverse PATENTEDHAY 4mm I 3.577.085

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QlUINAliti! REDUCTION STAGE AND FORWARD- REVERSE COR CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation-in-part of U.S. application Ser. Nos. 679,966 and 538,663 by the same inventor. U.S. Pat. application Ser. No. 679,966 in turn is a continuation-in-part of U.S. Pat. application Ser. No. 392,998, filed on Aug. 24, 1964 and entitled Arrangement For Counting Signals of Specific Significance," which application in turn is a continuation-in-part of U.S. Pat. application Ser. No. 279,039, filed on May 6, 1963 for Arrangement For Counting Signals Of Specific Significance," now abandoned.

BACKGROUND OF THE INVENTION This invention relates to quinary reduction stages for reducing the frequency of multiphase binary signal sequences by a factor of five, or, equivalently, increasing the period of such binary signal sequences by a factor of five. The invention further relates to the interconnection of such reduction stages to form forward and reverse decade counters.

More specifically, this invention relates to such quinary reduction stages for use with two-phase binary signal generator means which, for a continuous change of a physical quantity, are adapted to generate a primary combination signal consisting of a first predetermined cyclic sequence of possible signal combinations for a positive unit change of said physical quantity and a second sequence for a negative unit change of said physical quantity.

In U.S. Pat. No. 3,408,484, a counter for two-phase binary signal series is disclosed. The disclosed counter comprises DC coupled binary reduction stages for transferring binary signal series which are reduced in the ratio 2:1 relative to the input signal series. By reduction is meant frequency or repetition rate reduction or decrease.

Prior to the aforementioned patent application, counters for forward and reverse counting of binary signal series operated with the two-phase binary signal series produced by the analog-digital converter reduced either in the converter itself or in an ancillary circuit component connected to the input of the counter. The reduction of the two-phase binary signal series was into pulse series which were to be counted positively or forward and negatively or in reverse. A forward-reverse signal was provided to control the forward or reverse counting in the desired sense. The counters each comprised a series of pulse counter stages utilizing flip-flops or bistable multivibrators and including capacitors for circuit control during a change in circuit condition. Suitable logical circuitry such as AND gates were utilized with the flip-flops to switch the coupling components between the counter stages during the transmittal of the forward-reverse control signal from the forward stage to the reverse" stage.

The DC coupled binary reduction stages disclosed in the aforementioned patent have several significant advantages over the forward-reverse counters utilized theretofore. Since, in a preferred embodiment, the output signal series of each counter stage is a two-phase binary series which is the same as the two-phase signal series produced by the analog-digital converter and which has the same phase sequence as the signal series produced by said converter, and since only the pulse period is twice as long, conditions are the best possible for connecting the counter stages without interference with the overall circuit and without the need for special arrangements for adapting the repetition rate of the input signal series. Additive connection with input or output signal series from desired intermediate counter stages of other two-phase binary sigial series is facilitated and may be accomplished by a single two-phase conductor. The various signal series may then be added incrementally. The trigger time of the reduction stages comprising two flip-flops is considerably less than the trigger time of the theretofore utilized binary reduction stages comprising one flip-flop and storage capacitors. Due to the DC coupling of the binary reduction stages, there are no particular requirements for the form or configuration of the pulses, and variations in configuration of the pulses do not adversely affect the operation of the counter stages. The DC coupling of the reduction stages has the further advantage of permitting the frequency or repetition rate of the signal series to be counted to be considerably greater than is permissible when capacitor coupling is utilized and prevents a reversal of the counting sense during the transfer of a signal. An accurate count, free of interference and free of error, is obtained, due to the storage by the counter stages of whole pulse periods and not quarter or half periods of the pulses of the two-phase input signal series.

The principal object of the present invention is to provide a new and improved forward and reverse counter for a twophase binary signal series. The counter of the present invention is an improvement over the counter disclosed in the aforementioned patent and the counter of the present invention has all the aforementioned advantages of the disclosed counter but is considerably more simple in structure, utilizes considerably less components and has considerably greater technical facility than the counter disclosed in U.S. Pat. No. 3,408,484.

SUMMARY OF THE INVENTION This invention comprises logic network means for use with multiphase binary signal generator means which, for a continuous change of a physical quantity, are adapted to generate a primary combination signal consisting of a first predetermined cyclic sequence of possible signal combinations for a positive unit change of said quantity and a second sequence for a negative unit change of said physical quantity. It comprises a plurality of input lines corresponding in number to the number of phase of said primary combination signals. It further comprises the plurality of output lines corresponding in number to the number of said input lines. A plurality of bistable switching means, direct current coupled, and logically interconnected both mutually and to said input lines and output lines serve to generate a secondary combination signal, said secondary combination signal being the same type of multiphase binary signal as said primary combination signal, but having a secondary period which is a multiple of five of said primary combination signal period.

Decade reduction stages formed by use of either a single quinary stage, or a quinary stage in conjunction with a binary stage are also disclosed.

Further disclosed is a forward-reverse counter utilizing said decade reduction stages.

In order that the present invention may be readily carried into effect, it will now be described with reference to the accompanying drawings, wherein:

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a schematic diagram of an embodiment of a quinary reduction stage of the present invention;

FIG. 2 is a schematic diagram of an alternate embodiment of a quinary reduction stage of the present invention;

FIG. 3 is a forward-reverse counter utilizing the quinary stages of the present invention;

FIG. 4 shows the signals at the various points of the counter of FIG. 3',

FIG. 5 is a schematic diagram of an embodiment of a decade encoder which may be utilized as each of the decade encoders 87A, 87B, and 87C of FIG. 3; and

FIG. 6 is a schematic diagram of an embodiment of a decade encoder which may be used as the decade encoder of FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. I shows the preferred embodiment of a quinary reduction stage, which utilizes a substantially minimum number of components.

The DC coupled quinary reduction stage of FIG. 1 comprises a plurality of flip-

flops

11, 12, 13 and 14, having a plurality of AND

gates

15, 16, 17, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28, 29, 31 and 32, a plurality of OR

gates

33, 34, 35, 36, 37, 38, 39, 41 and 42, and a plurality of

inverters

43, 44, 45, 46, 47, 48, 49, 51, 52 and 53. These, as other logic circuits described herein, may be hydraulic elements as well as electronic or electrical elements, although the preferred embodiment described herein is electronic. The actual circuit leads are dispensed with in the interest of clarity of presentation; the connecting inputs and outputs being similarly identified. Four inputs X, X, Y and? are connected to inputs of the AND gates. The input X is connected to an input of each of the AND

gates

16, 19, 21, 22, 23, 27 and 28. The inputXis connected to an input of each of the AND

gates

15, 17, 13, 24, 25, 26 and 29. The input Y is connected to an input of each of the AND

gates

17, 19, 22, 24 and 32. The input Y is connected to an input of each of the AND

gates

18, 21, 23, 25 and 31.

Each of the AND gates, OR gates, inverters and flip-flops comprises any suitable arrangement for performing the desired functions, and such logical circuits and components are well known in the art. The output G of the inverter 43 is connected to an input of the OR gate 34 and the output H of the inverter 44 is connected to an input of the OR gate 33. The output of the AND gate is connected to an input of the OR gate 33 and the output of the AND gate 16 is connected to an input of the OR gate 34. The output G of the OR gate 33 is connected to the input of the inverter 43 and the output i of the OR gate 34 is connected to the input of the inverter 44. The inverters 43 and 44 and their corresponding circuitry operate together as a pair and comprise the flip-flop 11. The output G of the inverter 43 is connected to an input of the AND gate 21 of the flip'flop 12, to an input of the AND gate 22 of the flip-flop 13 and to an input of each of the AND

gates

27 and 29 of the flip-flop 14. The output 11 of the inverter 44 is connected to an input of the AND gate 17 of the flip-flop 12, to an input of an AND gate 25 of the flip-flop 13 and to an input of each of the AND

gates

26 and 23 of the flip-flop 14.

The output J of the inverter 45 is connected to an input of the OR gate 36 and the output K of the inverter 46 is connected to an input of the OR gate 35. The output of the AND gate 17 and the output of the AND gate 13 are connected to inputs of the OR gate 35 and the output of the AND gate 19 and the output of the AND gate 21 are connected to inputs of the OR gate 36. The output Totthe OR gate 35 is connected to the input of the inverter 45 and the outputii of the OR gate 36 is connected to the input of the inverter 46. The inverters 45 and 46 and their corresponding circuitry operate together as a pair and comprise the flip-flop 12. The output J of the inverter 45 is connected to an input of the AND gate 24 of the flip-flop 13 and to an input of the AND gate 31. The output 1% of the inverter 46 is connected to an input of the AND gate 23 of the flip-flop 13 and to an AND gate 32.

The output L of the inverter 47 is connected to an input of the OR gate 38 and the output M of the inverter 48 is connected to an input of the OR gate 37. The output of the AND gate 22 and the output of the AND gate 23 are connected to inputs of the OR gate 37 and the output of the AND gate 24 and the output of the AND gate 25 are connected to inputs of the OR gate 38. The output I: of the OR gate 37 is connected to the input of the inverter 47 and the outputT/iof the OR gate 38 is connected to the input of the inverter 43. The

inverters

47 and 48 and their corresponding circuitry operate together as a pair and comprise the flip-flop 13. The output L of the inverter 47 is connected to an input of the AND gate 19 of the flip-flop 12 and to an input of the AND gate 31. The output M of the inverter 48 is connected to an input of the AND gate 18 of the flip-flop 12 and to an input of the AND gate 32.

The output N of the inverter '49 is connected to an input of the OR gate 41 and the output 11 of the inverter 51 is connected to an input of the OR gate 39. The output of the AND gate 26 and the output of the AND gate 27 are connected to inputs of the OR gate 39 and the output of the AND gate 28 and the output of the AND gate 29 are connected to inputs of the OR gate 41. The output N of the OR gate 39 is connected to the input of the inverter 49 and the output 0 of the OR gate 41 is connected to the input of the inverter 51. The inverters 49 and 51 and their corresponding circuitry operate together as a pair and comprise the flip-flop 14. The output N of the inverter 49 is connected to an input of the AND gate 17 and to an input of the AND gate 21 of the flip-flop 12, and to an input of the AND gate 22 and to an input of the AND gate 25 of the flip-flop 13. The output 11 of the inverter 51 is connected to an input of the AND gate 15 and to an input of the AND gate 16 of the flip-flop 11.

The output P of the inverter 52 is directly connected to the input of the inverter 53. The output of the AND gate 31. and the output of the AND gate 32 are connected to the inputs of the OR gate 42. The output P of the OR gate 42 is connected to the input of the inverter 52. The output P of the inverter 52 is equal to the input 601' the inverter 53. The output I of the inverter 52 is connected to an input of the AND gate 15 and to an input or" the AND gate 16 of the flip-flop 11. The output Q of the inverter 53 is connected to an input of the AND gate 26, to an input of the AND gate 27, to an input of the AND gate 23 and to an input of the AND gate 29 of the flip-flop 14.

The DC coupled quinary reduction stage of FIG. 1 functions to relate combinations of two input signals in the inputs X and Y and combinations of the four flip-

flops

11, 12, 13 and 14, which provide the inputs of the flip-flops of succeeding reduction stages or storage stages. The relation of the combinations of the input signals in the inputs X and Y and the combinatrons of the fl1p-

flops

11, 12, 13 and 14 is illustrated in Table I.

TABLE I Pulse period X2 Y2 11 12 13 14 Quarter Half Whole 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 2 1 1 0 0 0 0 1 3 0 o 0 0 1 1 4 2 0 1 0 0 1 1 5 1 1 1 0 1 1 1 6 3 1 0 0 1 1 1 7 0 0 0 1 1 0 8 4 0 1 0 1 1 0v 9 2 1 1 1 1 1 0 10 5 1 0 1 1 1 0 11 0 0 1 1 1 1 12 6 o 1 1 1 1 1 13 3 1 1 1 1 0 1 14 7 1 0 1 1 0 1 15 0 0 1 0 0 1 1s 8 0 1 1 0 0 1 17 4 1 1 1 0 0 0 18 9 1 0 1 0 0 0 19 0 0 0 0 0 0 20 1o 0 1 0 0 0 0 21 5 1 1 0 0 0 1 22 u 1 0 0 0 0 1 23 0 0 0 0 1 1 24 12 0 1 0 0 1 1 25 6 1 1 0 1 1 1 2s 13 1 0 0 1 1 1 27 In Table I, the X and Y columns indicate combinations of two signals of a two-phase binary signal series shown as curves A and B of FIG. 4. The related combinations of the DC coupled flip-flops 1 ll, 12, 13 and 14 of the quinary reduction stage are shown in

columns

11, 12, 13 and 14 of Table I. The output pulses or signals of the quinary reduction stage are the same type of two-phase binary signal series as the input signals or pulses in the inputs X and Y except that the output signal pulse periods of each quinary stage are five times the input signal pulse periods. The quarter pulse periods, the half pulse periods and the whole pulse periods of the input signal series X and Y are indicated by consecutive numbers in the pulse period columns of Table I.

The

inverters

43, 44, 45, 46, 47, 48, 49, 51, 52 and 53 function not only to invert the outputs of their corresponding OR gates, but also to equalize the output loads. The inverter inputs are indicated as follows for the

inverters

43, 44, 45, 46, 47, 43, 49, 51, 52 and 53.

Inverter 43 Input OPX+H Inverter 44 llnput OPX+G Inverter 45 Input M( Y +HNT(Y+K Inverter 46 Input LXY+GNXY+J Inverter 47 Input KXY-i-GIQ(Y+M Inverter 48 Input JYE-HNXY-i-L Inverter 49 Input I-IQX+GQX+O Inverter 51 lnput= HQX+GQX+N Inverter 52 Input JL Y +KMY Inverter 53 Input P The outputs G, H, J and K of a stage are coupled to the inputs KY, Y and Y, respectively, of the next succeeding stage.

The

inverters

52 and 53 of FIG. 1 function to eliminate the need for diodes in the flip-flops. Any suitable logic circuitry which performs the indicated functions may be utilized instead of that shown in FIG. 1, but the circuitry shown is simpler in structure than such other circuitry.

The signal series illustrated as curves E and F of FIG. 4 are produced by the quinary stage of FIG. 1 as the outputs of the inverters 43 and 45 of the flip-flops 11 and 12 thereof when the inputs to said flip-flops are the signal series illustrated as curves C and D of FIG. 5. The signal series of curves C and D are a two-phase binary signal series as is the input signals of curves A and B of FIG. 5 except that the pulse periods of the signal series of curves C and D are twice the pulse periods of the input signals of curves A and B.

FIG. 2 shows an alternate embodiment of a quinary reduction stage. While this embodiment requires somewhat more components than the embodiment illustrated above, it is more suitable for mass production, since identical circuit components having identical numbers of inputs and outputs are used throughout.

Reference to FIG. 2 shows the four input lines labeled X, X, Y, Y. These are connected in pairs to two-input AND gates whose respective outputs are labeled N, O, P and Q respectively. These AND gates constitute auxiliary logic means and the output N, O, P and Q constitute the auxiliary input signals. As shown in this FIG., these auxiliary input signals are supplied to five flip-flops labeled FA, FB, FC, FD and FE respectively. It should be noted that these flip-flops are all mutually identical and that therefore only the logic circuitry of flip-flop at FA is shown. This logic circuitry consists of a primary channel, labeled first primary channel on the FIG., since the corresponding primary channel in flip-flop at B, at C, at D and at E constitute respectively the second, third, fourth and fifth primary channels. These primary channels each consist of two identical AND gates each of said AND gates having two inputs and one output. The output of these AND gates are fed to an OR gate which also receives a signal from one of the output lines. The output of the OR gate is then fed to an inverter labeled I whose output comprises one of the signals on the output lines. Specifically, for the first primary channel, this output is the output labeled A which corresponds to the input X to the next stage. It will be seen that the secondary channel output of flip-flop FA furnishes the signals X which is the inverse X input to the following stage. The second primary channel and second secondary channel, namely the cor responding channels in flip-flop FB furnish signals B and B respectively. These constitute auxiliary signals. Flip-flop F I furnishes signals C and C which constitute signals Y and Y which are the second phase input signals to the following stage. Further auxiliary signals and their inverses are furnished by flip-flops FD and FE. 7

The equations for the outputs N, 0', P' and Q of the auxlliary logic means in relation to the inputs X, X, Y, Y are as follows:

The equations for the primary and secondary channels of the various flip-flops are as follows:

Again, if the input signals to a quinary reduction stage which follow the above equation are the signals shown on lines C and D of FIG. 4, then the resultant outputs of such a quinary reduction stage will the signals shown in lines E and F of said FIG. 4. However, if signals are furnished to the system as shown in lines A and B of FIG. 4 which represent the signals x, and y in FIG. 3, these may be reduced in frequency by a binary stage as set forth in US. Pat. No. 3,408,484, thus yielding the signals of lines C and D. These may then be further reduced by a quinary stage according to this invention. The logic table for this condition is Table II wherein A and C signify the output signals which comprise the inputs to the following stage and correspond to signals x and y in FIG. 4. Table II is the following:

TABLEII Pe X2 Y2 X2 Y? A B c D E Pe X0 Y2 X2 Y2 A B o D E 0... 0LOL04 00L0L LL 0 L LL 0 L L 0 0 L L 0 0 L 00 L L 00 L L 0L L L 0L L L 1.. 0LOLL5 L0L0L LL L 0 LL L 0 L0 L 0 L0 L 0 p 00 0 0 00 0 0 0L 0 0 0L 0 0 2 0LO0L6 LoLoo LL 0 L LL 0 L L0 0 L L0 0 L 00 L L 00 L L 0L L L 0L L L a 0LLOL7 L0LL0 LL L 0 LL L 0 L0 L 0 L0 L 0 00 o 0 00 0 0 0L 0 0 0L 0 0 4.. 00LOL8 L0 0L0 LL 0 L LL 0 L L0 0 L L0 0 L Table ll-Continucd Pt X2 Y3 X3 Y2 A B C D E P9 X2 Y2 X2 Y3 A B C D E o L L 0 0 L L 0 L L L L L 0 L L L 0 0 L L L 0 L 0 L L L 0 L L L 0 L 0 L 0 L L L o m- 0 0 0 0 0 0 0 0 0 L 0 0 0 L 0 0 0. L 0 L o 0 r0 0 L 0 L 0 L L 0 L L L 0 L L 0 0 L L o o L 0 0 L L o o L L FIG. 4 shows a forward and reverse counter of the present invention. In FIG. 3, an analog-digital converter or binary encoder 61 produces a two-phase binary signal series x0, ya in its outputs 62 and 63 upon rotation in a determined direction, indicated by an arrow, of an input shaft 64. The binary signal series x0, yo produced by the analog-digital converter 61 is the same in form and phase as the signal series x2, y2 shown as the curves A and B of FIG. 4. if the input shaft 64 of the analogdigital converter is rotated in a direction opposite to the determined direction, the phase is varied so that the signal series x2 leads the signal series yZ instead of lagging it.

In FIG. 3, the outputs 62 and 63 of the analog-digital converter 61 are the inputs of a first quinary reduction stage 65A. The first quinary reduction stage 65A has

outputs

66 and 67 which are the inputs of a second quinary reduction stage 65B and in which signal series x1, y1 are provided. The second quinary reduction stage 6513 has outputs 68 and 69 which are the inputs of a first binary reduction stage 71A and in which signal series x2, y2 are provided. The first binary reduction stage 71A has outputs 72 and 73 which are the inputs of a third quinary reduction stage 65C and in which signal series x2, y2 are provided. The third quinary reduction stage 65C has

outputs

74 and 75 which are the inputs of a second binary reduction stage 71B and in which signal series x3, y3 are provided. The second binary reduction stage 71B has outputs 76 and 77 which are the inputs of a fourth quinary reduction stage 65D and in which signal series x3, y'3 are provided. The fourth quinary reduction stage 65D has

outputs

78 and 79 which are the inputs of a third binary reduction stage 71C and in which signal series xl, y? are provided. The third binary reduction stage 71C has outputs M and 32 which are the inputs of a fifth quinary reduction stage 65E and in which signmri es x4, y'4 are provided. The fifth quinary reduction stage 6513 has outputs 83 and M, in which signal series x5, y5 are provided, and which are the inputs of the next succeeding stage.

A decade encoder 85 is connected to an output 86 of the first quinary reduction stage 65A. A decade encoder 87A is connected to an output 88 of the second quinary reduction stage 65B. A decade encoder 873 is connected to an output 89 of the third quinary reduction stage 65C. A decade encoder 87C is connected to an output 91 of the fourth quinary reduction stage 65D, and so on.

Each of the binary reduction stages 71A, 71B, 71C, and so on may comprise any suitable binary reduction stage such as, for example, that disclosed in the aforementioned patent. Each of the quinary reduction stages 65A, 65B, 65C, 65D, 65E, and so on may comprise the quinary reduction stage of FIG. 1 or FIG. 2.

For decade counter operation of the forward and reverse counter of FIG. 3, the reduction ratio N is :1 or (2:1) (5:1 as shown in FIG. 4, where the signal series of the curves A and B are initially reduced in the ratio 2:1, as shown in the curves C and D. The signal series of the curves C and D are then reduced in the ratio 5:1 to produce the signal series of the curves E and F which thus have a pulse period 10 times longer than the signal series of the curves A and B.

The decade encoder 85 is controlled by the first quinary reduction stage 65A to provide a visual indication of the quarter pulse periods of the signal series x0, ytl produced by the analog-digital converter 61. The visual indication provided by the decade encoder is presented in a 4-bit code, for example, by four

lamps

92A, 92B, 92C and 92D, each of which represents a bit of the visual code. The 4-bit code may be indicated in accordance with Table III.

TABLE III Lamp Lamp Lamp Lamp Decimal Number 92D 92C 92B 92A In Table III, the lamp 92A represents the digit 1, the lamp 923 represents the digit 2, the lamp 92C represents the digit 2 and the lamp 921) represents the digit 4.

The second quinary reduction stage 658 of the counter of FIG. 3 controls the decade encoder 87A to provide a visual indication of the half pulse periods of the signal series x1, yl produced by the first quinary reduction stage 65A. The visual indication provided by the decade encoder 87A is presented in a 4-bit code, for example, by four lamps 93A, 93B, 93C and 93D, each of which represents a bit of the visual code. The decade encoder 67A thus advances the lamps 93A, 93B, 93C and 93D in tens, rather than in units as does the decade encoder 85. Thus, the lamps 93A, 93B, 93C and 93D indicate in 10 quarter pulse periods of the signal series x0, yo.

The decade encoders 87B and 87C are the same as the decade encoder 87A, and provide visual indications of 100 quarter pulse periods and 1000 quarter pulse periods, respectively, of the signal series x0, ya. This is due to the operation of the first binary reduction stage 71A and the second binary reduction stage 71B connected to the inputs of the third and fourth quinary reduction stages 65C and 65D, respectively. Four indicator lamps 94A, 94B, 94C and 94D are connected to the output of the decade encoder 87B and four indicator lamps 95A, 95B, 95C and 95D are connected to the output of the decade encoder 87C.

The visual indications need not be provided by four lamp units, but may be provided by any suitable means in any suitable code such as, for example, dekatron-type tubes which provide direct indications. A

FIG. 5 shows a decade encoder which may be utilized as each of the decade encoders 87A, 87B and 87C of FIG. 3. The diagram of FIG. 5 is presented in the same manner as the diagram of FIG. 1, without the actual circuit leads being shown, but with connected inputs and outputs being similarly identified. In FIG. 5, four

inverters

101, 102, 103 and 104, four AND

gates

105, 106, 107 and 108, and two OR

gates

109 and 1 11 are connected as shown. Each of the AND gates, OR gates and inverters comprises any suitable arrangement for performing the desired functions, and such logical circuits are well known in the art.

The inverter, and other inputs are indicated as follows for the inputs X, Y, G and H and for the

inverters

102 and 104.

Input X=Al InputY=A1 Input G=A4 Input I-I=A4 Inverter 102 lnput= JX+HM Inverter 104 lnput= I-IK-l-GL I FIG. 6 shows a decade encoder which may be utilized as the decade encoder 85 of FIG. 3. The diagram of FIG. 6 is presented in the same manner as the diagrams of FIGS. 1 and 3, without the actual leads being shown, but with connected inputs and outputs being similarly identified. In FIG. 6, eight

inverters

112, 113, 114, 115, 116, 117, 118 and 119, 14 and

gates

121, 122, 123, 124, 125, 126, 127, 128, 129, 131, 132, 133, 134 and 135, and four OR

gates

136, 137, 138 and 139 are connected as shown. Each of the AND gates, OR gates and inverters comprises any suitable arrangement for perfomiing the desired functions, and such logic circuits are well known in. the art.

The inverter inputs are indicated as follows for the inverters 113,115, 117 and 119.

Inverter 1 13 Input=XY+X Y- I Inverter 115 lnput= NXY+NY Y +HLO+GMO Inverter 117 Input GMY+HLY+JPY+ I PX Inverter 119 Input= HF-l-GK+KLY+J MY In the forward and reverse counter of FIG. 3, two binary reduction stages are eliminated, since they are not connected in the inputs of the first and second quinary reduction stages 65A and 658, due to the use of the decade encoders 85 and 87A. The decade encoder 85 also provides, as hereinbefore disclosed, visual or other indications of the quarter pulse periods of the signal series x0, yo produced by the analogdigital converter 61.

While the invention has been described by means of a specific example and in a specific embodiment, I do not wish to be limited thereto, for obvious modifications will occur to those skilled in the art without departing from the spirit and scope of the invention.

What is claimed as new and desired to be protected by Letters Patent is set forth in the appended claims.

I claim:

1. Quinary reduction stage, comprising, in combination, two-phase signal generator means furnishing a primary combination' signal comprising a first and second binary signal sequence having a predetermined period, said second binary signal sequence having a predetermined phase shift relative to said first binary signal sequence, at a first and second signal generator output respectively; a first and second output line; and a plurality of direct current coupled logic circuits including means for connecting said first and second signal generator outputs with said first and second output lines for generating a secondary combination signal on said output lines, said secondary combination signal comprising a first and second binary signal sequence having a phase shift corresponding to said predetermined phase shift, but having a secondary period which is five times said predetermined period.

2. Quinary reduction stage as set forth in claim 1, wherein said two-phase signal generator means further comprise a third and fourth signal generator output furnishing, respectively, the inverse of said first and second binary signal sequence of said primary combination signal; a third and fourth output line furnishing, respectively, the inverse of the first and second binary signal sequence of said secondary combination signal; and wherein said plurality of logic circuits comprise a first and second primary circuit channel furnishing, respectively, said first and second binary signal sequence of said secondary combination signal, and a third, fourth and fifth primary circuit channel including means for furnishing, respectively, a first primary auxiliary signal, a second primary auxiliary signal, and a third primary auxiliary signal.

3. Quinary reduction stage as set forth in claim 2, also comprising at least a first, second, third, and fourth secondary circuit channel, each channel including means for logically interconnecting the corresponding primary circuit channel and at least one other of said circuit channels, such that each of said secondary circuit channels furnishes a secondary channel output signal which is the inverse of the signal furnished by the corresponding primary circuit channel, each pair of corresponding primary and secondary channels thus constituting a flip-flop.

4. Quinary reduction stage as set forth in claim 3, wherein said primary and secondary circuit channels are interconnected and connected to said input lines and to said output lines such as to satisfy simultaneously the following Boolean sr a g OPX+ H1st secondary circuit channel.

1:1 OgIg-l- G-1st primary circuit channel.

J MXY+ HNXY K2nd secondary circuit channel. If LXX-l- GNXY-l- J 2nd primary circuit channel. I KXY+ GNX+ M3rd secondary circuit channel. M J XY-l- HNXY+ L3rd primary circuit channel. N HQX GQX O4th secondary circuit channel. Q HQ X GQX N- ith primary circuit channel. 1:: J LY+ KMY-5th primary circuit channel.

wherein:

inputs to next stage.

where X, Y, and X,, Y,, respectively signify the instantaneous signals in said input lines and said output lines respectively, and wherein Y, Y, and X Y, signify the corresponding inverse (NOT) signals.

5. Quinary reduction stage as set forth in claim 2, wherein all of said primary circuit channels are identical; also comprising first, second, third and fourth mutually identical auxiliary logic means, interconnected between said signal generator output and said primary circuit channels and including means for furnishing auxiliary input signals to said primary circuit channels as a function of combinations of conditions on said input lines.

6. Quinary reduction stage as set forth in claim 5, wherein said identical auxiliary logic means each comprise an AND gate, each of said AND gates having two inputs, each of said inputs being connected to said signal generator outputs such that said auxiliary input signals each correspond to one of the four possible condition combinations at said signal generator outputs.

7. Quinary reduction stage as set forth in claim 6, also comprising first, second, third, fourth and fifth secondary circuit channels, each identical to the corresponding primary circuit channel, each interconnected to said auxiliary logic means, said primary circuit channels and said output lines with direct current coupling, such that each secondary circuit channel furnishes a secondary circuit channel output signal which is the inverse of the corresponding primary circuit channel output signal.

8. Quinary reduction stage as set forth in claim 7, wherein each of said circuit channels comprises two channel AND gates; an OR gate series connected to said two channel AND gates; and an inverter gate series connected to said OR gate.

9. Quinary reduction stage as set forth in claim 7, wherein said auxiliary logic means outputs are designated N, O, P and Q; and wherein said auxiliary logic means simultaneously satisfy the following Boolean equations:

o'=x Y Q'=X Y wherein each of said primary circuit channels has a corresponding secondary circuit channel, identical to it, connected to it suchthat said primary circuit channels and seconwherein A,a=A; C,c=@ constitute the first and second phase of said secondary combination signal respectively, while B, D, and E constitute auxiliary signals.

10. Quinary reduction stage as set forth in claim 1, wherein said logic circuits comprise hydraulic elements.

ll 1. A forward-reverse counter, comprising, in combination, means for furnishing a two-phase binary signal sequence having a predetermined phase shift between said two phases; and a plurality of direct current coupled reduction stages connected in cascade to said means for furnishing a two-phase binary signal sequence, each of said reduction stages including means for furnishing, in response to an input two-phase binary signal sequence, an output binary signal sequence having the same phase shift as said input binary signal sequence but a period which is an integral multiple of the period of said input two-phase binary signal sequence, at least one of said direct current coupled reduction stages being a quinary reduction stage.

12. A forward-reverse counter as set forth in claim Ill, further comprising a direct current coupled binary reduction stage connected in cascade with said direct current coupled quinary reduction stage, thereby forming a decade reduction stage.

13. A forward-reverse counter for use with multiphase binary signal generator means which, for a continuous change of a physical quantity, generate a primary combination signal consisting of a first predetermined cyclic sequence of possible signal combinations in a plurality of phases for a positive unit change of said quantity and a second sequence for a negative unit change of said physical quantity, each individual change of signal combinations signifying a change of said quantity corresponding to a fraction of said unit change, comprising, in combination, a plurality of input lines, corresponding in number to the number of phases of said primary combination signal, connected to the output of said binary signal generator means; a plurality of output lines corresponding in number to the number of said input lines; a direct current coupled reduction stage interconnecting said input lines and said output lines and including means for generating a secondary combination signal on said output lines having the same sequence of possible signal combinations as said primary combination signal, but having a secondary period which is an integral multiple of the period of said primary combination signal; first counting means having inputs connected to said input lines for counting said individual changes of signal combinations in said primary combination signal and furnishing a first counting signal in response thereto; and second counting means having inputs connected to said output lines for counting a predetermined fraction of individual changes of signal combinations in said secondary combination signal, whereby the ratio of said second counting signal to said first counting signal corresponds to said integral multiple divided by said predeterned a qn. t

14. A forward-reverse counter as set forth in claim 13, wherein said direct current coupled reduction stage is a quin ary reduction stage; wherein said plurality of phases comprises two phases; wherein said first predetermined cyclic sequence of possible signal combinations in said two phases comprises a sequence of four possible signal combinations; wherein said first counting means count each of said four signal combinations in each period of said primary combination signal; wherein said second counting means count alternate ones of said individual changes of signal combinations in said secondary combination signal, whereby a count on said second counting means represents 10 counts in said first counting means.

Claims

1. Quinary reduction stage, comprising, in combination, twophase signal generator means furnishing a primary combination signal comprising a first and second binary signal sequence having a predetermined period, said second binary signal sequence having a predetermined phase shift relative to said first binary signal sequence, at a first and second signal generator output respectively; a first and second output line; and a plurality of direct current coupled logic circuits including means for connecting said first and second signal generator outputs with said first and second output lines for generating a secondary combination signal on said output lines, said secondary combination signal comprising a first and second binary signal sequence having a phase shift corresponding to said predetermined phase shift, but having a secondary period which is five times said predetermined period.

4. Quinary reduction stage as set forth in claim 3, wherein said primary and secondary circuit channels are interconnected and connected to said input lines and to said output lines such as to satisfy simultaneously the following Boolean equations:

9. Quinary reduction stage as set forth in claim 7, wherein said auxiliary logic means outputs are designated N'', O'', P'' and Q''; and wherein said auxiliary logic means simultaneously satisfy the following Boolean equations: N'' X Y P'' X Y O'' X Y Q'' X Y wherein each of said primary circuit channels has a corresponding secondary circuit channel, identical to it, connected to it such that said primary circuit channels and secondary circuit channels simultaneously satisfy the following Boolean equations: A BN'' +EO''+a a bP''+eQ''+A B CN''+AO''+b b cP''+aQ''+B C DN''+BO''+c c dP''+bQ''+C D EN''+CO''+d d eP''+cQ''+D E AN''+DO''+e e aP'' dQ''+D wherein A,a A; C,c C constitute the first and second phase of said secondary combination signal respectively, while B, D, and E constitute auxiliary signals.

11. A forward-reverse counter, comprising, in combination, means for furnishing a two-phase binary signal sequence having a predetermined phase shift between said two phases; and a plurality of direct current coupled reduction stages connected in cascade to said means for furnishing a two-phase binary signal sequence, each of said reduction stages including means for furnishing, in response to an input two-phase binary signal sequence, an output binary signal sequence having the same phase shift as said input binary signal sequence but a period which is an integral multiple of the period of said input two-phase binary signal sequence, at least one of said direct current coupled reduction stages being a quinary reduction stage.

12. A forward-reverse counter as set forth in claim 11, further comprising a direct current coupled binary reduction stage connected in cascade with said direct current coupled quinary reduction stage, thereby forming a decade reduction stage.

13. A forward-reverse counter for use with multiphase binary signal generator means which, for a continuous change of a physical quantity, generate a primary combination signal consisting of a first predetermined cyclic sequence of possible signal combinations in a plurality of phases for a positive unit change of said quantity and a second sequence for a negative unit change of said physical quantity, each individual change of signal combinations signifying a change of said quantity corresponding to a fraction of said unit change, comprising, in combination, a plurality of input lines, corresponding in number to the number of phases of said primary combination signal, connected to the output of said binary signal generator means; a plurality of output lines corresponding in number to the number of said input lines; a direct current coupled reduction stage interconnecting said input lines and said output lines and including means for generating a secondary combination signal on said output lines having the same sequence of possible signal combinations as said primary combination signal, but having a secondary period which is an integral multiple of the period of said primary combination signal; first counting means having inputs connected to said input lines for counting said individual changes of signal combinations in said primary combination signal and furnishing a first counting signal in response thereto; and second counting means having inputs connected to said output lines for counting a predetermined fraction of individual changes of signal combinations in said secondary combination signal, whereby the ratio of said second counting signal to said first counting signal corresponds to said integral multiple divided by said predetermined fraction.

14. A forward-reverse counter as set forth in claim 13, wherein said direct current coupled reduction stage is a quinary reduction stage; wherein said plurality of phases comprises two phases; wherein said first predetermined cyclic sequence of possible signal combinations in said two phases comprises a sequence of four possible signal combinations; wherein said first counting means count each of said four signal combinations in each period of said primary combination signal; wherein said second counting means count alternate ones of said individual changes of signal combinations in said secondary combination signal, whereby a count on said second countiNg means represents 10 counts in said first counting means.