CA2491923A1 - Memory controller with adaptive processor interface port - Google Patents

Memory controller with adaptive processor interface port Download PDF

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Publication number
CA2491923A1
CA2491923A1 CA002491923A CA2491923A CA2491923A1 CA 2491923 A1 CA2491923 A1 CA 2491923A1 CA 002491923 A CA002491923 A CA 002491923A CA 2491923 A CA2491923 A CA 2491923A CA 2491923 A1 CA2491923 A1 CA 2491923A1
Authority
CA
Canada
Prior art keywords
memory
bus
adaptive processor
computing system
memory controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002491923A
Other languages
English (en)
French (fr)
Inventor
Jon M. Huppenthal
Thomas R. Seeman
Lee A. Burton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SRC Computers LLC
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2491923A1 publication Critical patent/CA2491923A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
CA002491923A 2002-10-29 2003-10-24 Memory controller with adaptive processor interface port Abandoned CA2491923A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/282,986 2002-10-29
US10/282,986 US7003593B2 (en) 1997-12-17 2002-10-29 Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port
PCT/US2003/033941 WO2004040413A2 (en) 2002-10-29 2003-10-24 Memory controller with adaptive processor interface port

Publications (1)

Publication Number Publication Date
CA2491923A1 true CA2491923A1 (en) 2004-05-13

Family

ID=32228794

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002491923A Abandoned CA2491923A1 (en) 2002-10-29 2003-10-24 Memory controller with adaptive processor interface port

Country Status (6)

Country Link
US (1) US7003593B2 (enExample)
EP (1) EP1559021A4 (enExample)
JP (1) JP2006505046A (enExample)
AU (1) AU2003286693A1 (enExample)
CA (1) CA2491923A1 (enExample)
WO (1) WO2004040413A2 (enExample)

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US9177646B2 (en) 2013-05-06 2015-11-03 International Business Machines Corporation Implementing computational memory from content-addressable memory
US10741226B2 (en) 2013-05-28 2020-08-11 Fg Src Llc Multi-processor computer architecture incorporating distributed multi-ported common memory modules
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Also Published As

Publication number Publication date
EP1559021A2 (en) 2005-08-03
JP2006505046A (ja) 2006-02-09
AU2003286693A1 (en) 2004-05-25
WO2004040413A2 (en) 2004-05-13
WO2004040413A3 (en) 2004-08-19
EP1559021A4 (en) 2006-12-06
US20030061432A1 (en) 2003-03-27
US7003593B2 (en) 2006-02-21

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Legal Events

Date Code Title Description
FZDE Discontinued