JP2006505046A - 適応プロセッサインターフェイスポートを用いてハイブリッド処理システム内で緊密結合するためのコンピュータシステムアーキテクチャおよびメモリコントローラ - Google Patents

適応プロセッサインターフェイスポートを用いてハイブリッド処理システム内で緊密結合するためのコンピュータシステムアーキテクチャおよびメモリコントローラ Download PDF

Info

Publication number
JP2006505046A
JP2006505046A JP2004548488A JP2004548488A JP2006505046A JP 2006505046 A JP2006505046 A JP 2006505046A JP 2004548488 A JP2004548488 A JP 2004548488A JP 2004548488 A JP2004548488 A JP 2004548488A JP 2006505046 A JP2006505046 A JP 2006505046A
Authority
JP
Japan
Prior art keywords
memory
bus
adaptive processor
computing system
memory controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2004548488A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006505046A5 (enExample
Inventor
ハッペンサール，ジョン・エム
シーマン，トーマス・アール
バートン，リー・エイ
Original Assignee
エス・アール・シィ・コンピューターズ・インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by エス・アール・シィ・コンピューターズ・インコーポレイテッド filed Critical エス・アール・シィ・コンピューターズ・インコーポレイテッド
Publication of JP2006505046A publication Critical patent/JP2006505046A/ja
Publication of JP2006505046A5 publication Critical patent/JP2006505046A5/ja
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP2004548488A 2002-10-29 2003-10-24 適応プロセッサインターフェイスポートを用いてハイブリッド処理システム内で緊密結合するためのコンピュータシステムアーキテクチャおよびメモリコントローラ Withdrawn JP2006505046A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/282,986 US7003593B2 (en) 1997-12-17 2002-10-29 Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port
PCT/US2003/033941 WO2004040413A2 (en) 2002-10-29 2003-10-24 Memory controller with adaptive processor interface port

Publications (2)

Publication Number Publication Date
JP2006505046A true JP2006505046A (ja) 2006-02-09
JP2006505046A5 JP2006505046A5 (enExample) 2006-12-14

Family

ID=32228794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004548488A Withdrawn JP2006505046A (ja) 2002-10-29 2003-10-24 適応プロセッサインターフェイスポートを用いてハイブリッド処理システム内で緊密結合するためのコンピュータシステムアーキテクチャおよびメモリコントローラ

Country Status (6)

Country Link
US (1) US7003593B2 (enExample)
EP (1) EP1559021A4 (enExample)
JP (1) JP2006505046A (enExample)
AU (1) AU2003286693A1 (enExample)
CA (1) CA2491923A1 (enExample)
WO (1) WO2004040413A2 (enExample)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7565469B2 (en) * 2004-11-17 2009-07-21 Nokia Corporation Multimedia card interface method, computer program product and apparatus
US8909872B1 (en) 2006-10-31 2014-12-09 Hewlett-Packard Development Company, L. P. Computer system with coherent interconnection
US8145749B2 (en) * 2008-08-11 2012-03-27 International Business Machines Corporation Data processing in a hybrid computing environment
US8141102B2 (en) * 2008-09-04 2012-03-20 International Business Machines Corporation Data processing in a hybrid computing environment
US7984267B2 (en) * 2008-09-04 2011-07-19 International Business Machines Corporation Message passing module in hybrid computing system starting and sending operation information to service program for accelerator to execute application program
US8230442B2 (en) 2008-09-05 2012-07-24 International Business Machines Corporation Executing an accelerator application program in a hybrid computing environment
US8191072B2 (en) * 2008-12-22 2012-05-29 International Business Machines Corporation System and method for shifting workloads across platform in a hybrid system
US8458466B2 (en) * 2008-12-22 2013-06-04 International Business Machines Corporation System and method for handling cross-platform system call in a hybrid system
US8621207B2 (en) 2008-12-23 2013-12-31 International Business Machines Corporation System and method for handling cross-platform system call with shared page cache in hybrid system
US8493979B2 (en) * 2008-12-30 2013-07-23 Intel Corporation Single instruction processing of network packets
US8527734B2 (en) 2009-01-23 2013-09-03 International Business Machines Corporation Administering registered virtual addresses in a hybrid computing environment including maintaining a watch list of currently registered virtual addresses by an operating system
US9286232B2 (en) * 2009-01-26 2016-03-15 International Business Machines Corporation Administering registered virtual addresses in a hybrid computing environment including maintaining a cache of ranges of currently registered virtual addresses
US8843880B2 (en) * 2009-01-27 2014-09-23 International Business Machines Corporation Software development for a hybrid computing environment
US8255909B2 (en) * 2009-01-28 2012-08-28 International Business Machines Corporation Synchronizing access to resources in a hybrid computing environment
US8001206B2 (en) * 2009-01-29 2011-08-16 International Business Machines Corporation Broadcasting data in a hybrid computing environment
US20100191923A1 (en) * 2009-01-29 2010-07-29 International Business Machines Corporation Data Processing In A Computing Environment
US9170864B2 (en) * 2009-01-29 2015-10-27 International Business Machines Corporation Data processing in a hybrid computing environment
US8010718B2 (en) * 2009-02-03 2011-08-30 International Business Machines Corporation Direct memory access in a hybrid computing environment
US8037217B2 (en) * 2009-04-23 2011-10-11 International Business Machines Corporation Direct memory access in a hybrid computing environment
US8180972B2 (en) * 2009-08-07 2012-05-15 International Business Machines Corporation Reducing remote reads of memory in a hybrid computing environment by maintaining remote memory values locally
US9417905B2 (en) * 2010-02-03 2016-08-16 International Business Machines Corporation Terminating an accelerator application program in a hybrid computing environment
US8578132B2 (en) * 2010-03-29 2013-11-05 International Business Machines Corporation Direct injection of data to be transferred in a hybrid computing environment
US9015443B2 (en) 2010-04-30 2015-04-21 International Business Machines Corporation Reducing remote reads of memory in a hybrid computing environment
US8489784B2 (en) * 2010-12-31 2013-07-16 Silicon Image, Inc. Adaptive interconnection scheme for multimedia devices
US20130157639A1 (en) 2011-12-16 2013-06-20 SRC Computers, LLC Mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption
CN104303167B (zh) * 2012-05-08 2018-01-23 马维尔国际贸易有限公司 计算机系统和存储器管理的方法
JP6263836B2 (ja) * 2013-01-15 2018-01-24 オムロン株式会社 制御装置および制御方法
US9177646B2 (en) 2013-05-06 2015-11-03 International Business Machines Corporation Implementing computational memory from content-addressable memory
US10741226B2 (en) 2013-05-28 2020-08-11 Fg Src Llc Multi-processor computer architecture incorporating distributed multi-ported common memory modules
US9530483B2 (en) 2014-05-27 2016-12-27 Src Labs, Llc System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem
US9153311B1 (en) 2014-05-27 2015-10-06 SRC Computers, LLC System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers
US9411613B1 (en) 2015-04-22 2016-08-09 Ryft Systems, Inc. Systems and methods for managing execution of specialized processors
US9542244B2 (en) 2015-04-22 2017-01-10 Ryft Systems, Inc. Systems and methods for performing primitive tasks using specialized processors
US9411528B1 (en) 2015-04-22 2016-08-09 Ryft Systems, Inc. Storage management systems and methods

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4453214A (en) * 1981-09-08 1984-06-05 Sperry Corporation Bus arbitrating circuit
JPS58200323A (ja) * 1982-05-14 1983-11-21 Nec Corp 入出力処理装置
US4730268A (en) * 1985-04-30 1988-03-08 Texas Instruments Incorporated Distributed bus arbitration for a multiprocessor system
JPS626366A (ja) * 1985-07-03 1987-01-13 Hitachi Ltd 記憶制御方式
AU598101B2 (en) * 1987-02-27 1990-06-14 Honeywell Bull Inc. Shared memory controller arrangement
US4974148A (en) * 1987-07-06 1990-11-27 Motorola Computer X, Inc. Bus arbiter with equitable priority scheme
KR890007159A (ko) * 1987-10-30 1989-06-19 미다 가쓰시게 데이타 처리장치 및 그것을 갖는 데이타 처리 시스템
AU616213B2 (en) * 1987-11-09 1991-10-24 Tandem Computers Incorporated Method and apparatus for synchronizing a plurality of processors
DE68920388T2 (de) * 1988-09-19 1995-05-11 Fujitsu Ltd Paralleles Rechnersystem mit Verwendung eines SIMD-Verfahrens.
CA2011935A1 (en) * 1989-04-07 1990-10-07 Desiree A. Awiszio Dual-path computer interconnect system with four-ported packet memory control
EP0459233A3 (en) * 1990-05-29 1992-04-08 National Semiconductor Corporation Selectively locking memory locations within a microprocessor's on-chip cache
US5194895A (en) * 1991-09-13 1993-03-16 Xerox Corporation Printing machine adaptive setup
JPH05181793A (ja) * 1991-12-27 1993-07-23 Fujitsu Ltd Ｓｃｓｉバス制御方法
US5802290A (en) * 1992-07-29 1998-09-01 Virtual Computer Corporation Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed
US5414857A (en) * 1992-10-02 1995-05-09 Ast Research, Inc. Adaptive processor interface operable with different types of processors
US6052773A (en) * 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5570040A (en) * 1995-03-22 1996-10-29 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5696910A (en) * 1995-09-26 1997-12-09 Intel Corporation Method and apparatus for tracking transactions in a pipelined bus
US5903771A (en) * 1996-01-16 1999-05-11 Alacron, Inc. Scalable multi-processor architecture for SIMD and MIMD operations
US5949762A (en) * 1996-01-24 1999-09-07 Telebit Corporation Apparatus and method for processing multiple telephone calls
US5737766A (en) * 1996-02-14 1998-04-07 Hewlett Packard Company Programmable gate array configuration memory which allows sharing with user memory
EP0978051A1 (en) * 1996-06-21 2000-02-09 Mirage Technologies, Inc. Dynamically reconfigurable hardware system for real-time control of processes
US5892962A (en) * 1996-11-12 1999-04-06 Lucent Technologies Inc. FPGA-based processor
US6118462A (en) * 1997-07-01 2000-09-12 Memtrax Llc Computer system controller having internal memory and external memory control
US6078736A (en) * 1997-08-28 2000-06-20 Xilinx, Inc. Method of designing FPGAs for dynamically reconfigurable computing
US6023748A (en) * 1997-09-12 2000-02-08 Adaptec, Inc. Multiple client memory arbitration system capable of operating multiple configuration types
US6226776B1 (en) * 1997-09-16 2001-05-01 Synetry Corporation System for converting hardware designs in high-level programming language to hardware implementations
US6339819B1 (en) * 1997-12-17 2002-01-15 Src Computers, Inc. Multiprocessor with each processor element accessing operands in loaded input buffer and forwarding results to FIFO output buffer
US6076152A (en) * 1997-12-17 2000-06-13 Src Computers, Inc. Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
US6567426B1 (en) * 1998-03-05 2003-05-20 Silicon Graphics, Inc. Preemptive timer multiplexed shared memory access
US6414391B1 (en) * 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6192439B1 (en) * 1998-08-11 2001-02-20 Hewlett-Packard Company PCI-compliant interrupt steering architecture
US6128731A (en) * 1998-10-21 2000-10-03 Silicon Graphics, Inc. Advanced boot sequence for an +86 computer system that maintains expansion card device compatibility
JP3616518B2 (ja) * 1999-02-10 2005-02-02 日本電気株式会社 プログラマブルデバイス
US6442597B1 (en) * 1999-07-08 2002-08-27 International Business Machines Corporation Providing global coherence in SMP systems using response combination block coupled to address switch connecting node controllers to memory
US6434636B1 (en) * 1999-10-31 2002-08-13 Hewlett-Packard Company Method and apparatus for performing high bandwidth low latency programmed I/O writes by passing tokens
US6446145B1 (en) * 2000-01-06 2002-09-03 International Business Machines Corporation Computer memory compression abort and bypass mechanism when cache write back buffer is full
US6496971B1 (en) * 2000-02-07 2002-12-17 Xilinx, Inc. Supporting multiple FPGA configuration modes using dedicated on-chip processor
US6654818B1 (en) * 2000-06-22 2003-11-25 International Business Machines Corporation DMA access authorization for 64-bit I/O adapters on PCI bus
US6874039B2 (en) * 2000-09-08 2005-03-29 Intel Corporation Method and apparatus for distributed direct memory access for systems on chip
US6715094B2 (en) * 2000-12-20 2004-03-30 Intel Corporation Mult-mode I/O interface for synchronizing selected control patterns into control clock domain to obtain interface control signals to be transmitted to I/O buffers
US6441483B1 (en) * 2001-03-30 2002-08-27 Micron Technology, Inc. Die stacking scheme

Also Published As

Publication number Publication date
EP1559021A2 (en) 2005-08-03
CA2491923A1 (en) 2004-05-13
AU2003286693A1 (en) 2004-05-25
WO2004040413A2 (en) 2004-05-13
WO2004040413A3 (en) 2004-08-19
EP1559021A4 (en) 2006-12-06
US20030061432A1 (en) 2003-03-27
US7003593B2 (en) 2006-02-21

Similar Documents

Publication Publication Date Title
JP2006505046A (ja) 適応プロセッサインターフェイスポートを用いてハイブリッド処理システム内で緊密結合するためのコンピュータシステムアーキテクチャおよびメモリコントローラ
TWI869578B (zh) 用於計算的系統及方法
KR100271336B1 (ko) 주변구성요소 내부접속 버스상의 기능을 향상시키는 장치 및방법
RU2140667C1 (ru) Компьютерная система, имеющая шинный интерфейс
US6182178B1 (en) Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across a PCI host bridge supporting multiple PCI buses
US6330647B1 (en) Memory bandwidth allocation based on access count priority scheme
US6167476A (en) Apparatus, method and system for accelerated graphics port bus bridges
US6098134A (en) Lock protocol for PCI bus using an additional "superlock" signal on the system bus
JP4589384B2 (ja) 高速メモリモジュール
US6131135A (en) Arbitration method for a system with two USB host controllers
JP2000082035A (ja) 様々な周波数動作をサポ―トする複数の周辺構成要素相互接続バスをサポ―トする方法およびシステム
KR19990077461A (ko) 컴퓨터시스템내의단일주변장치연결부(ｐｃｉ)호스트브리지에의해다수의ｐｃｉ버스를지원하는방법및시스템
US20140297967A1 (en) Inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline
US6052754A (en) Centrally controlled interface scheme for promoting design reusable circuit blocks
US7565461B2 (en) Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
KR100807443B1 (ko) 기회적 판독 완료 결합
CN117561505A (zh) 用于动态地配置设备结构的系统、方法、装置和架构
EP1089501B1 (en) Arbitration mechanism for packet transmission
US8341360B2 (en) Method and apparatus for memory write performance optimization in architectures with out-of-order read/request-for-ownership response
US11537539B2 (en) Acceleration of data between a network and local I/O in a NUMA system
EP1231540A2 (en) Direct memory access controller
JPH02130662A (ja) 情報処理システム
US5933648A (en) Configurable arbitration device for controlling the access of components to an arbiter or the like based on a control input
US6377581B1 (en) Optimized CPU-memory high bandwidth multibus structure simultaneously supporting design reusable blocks
KR100475438B1 (ko) 데이터 버스 시스템 및 버스간 크로스 액세스 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061017

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061017

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20070320