CA2193098A1 - Preparation of Semiconductor Substrates - Google Patents

Preparation of Semiconductor Substrates

Info

Publication number
CA2193098A1
CA2193098A1 CA2193098A CA2193098A CA2193098A1 CA 2193098 A1 CA2193098 A1 CA 2193098A1 CA 2193098 A CA2193098 A CA 2193098A CA 2193098 A CA2193098 A CA 2193098A CA 2193098 A1 CA2193098 A1 CA 2193098A1
Authority
CA
Canada
Prior art keywords
substrate
preparation
promote
epitaxial layers
subsequent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2193098A
Other languages
French (fr)
Other versions
CA2193098C (en
Inventor
Paul Charles Spurdens
Mark Andrew Salter
Michael John Harlow
David John Newson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
British Telecommunications PLC
Original Assignee
Paul Charles Spurdens
Mark Andrew Salter
Michael John Harlow
David John Newson
British Telecommunications Public Limited Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Paul Charles Spurdens, Mark Andrew Salter, Michael John Harlow, David John Newson, British Telecommunications Public Limited Company filed Critical Paul Charles Spurdens
Publication of CA2193098A1 publication Critical patent/CA2193098A1/en
Application granted granted Critical
Publication of CA2193098C publication Critical patent/CA2193098C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02392—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02461—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02581—Transition metal or rare earth elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

An indium phosphide semiconductor substrate (10) is prepared for subsequent growth of epitaxial layers (12 to 16) to form a semiconductor device (5). In the preparation, the substrate (10) is first annealed to promote any tendency for surface accumulation of impurity atoms by diffusion from the substrate and to promote impurity atom removal from the surface of the substrate. The substrate (10) is then surface etched to remove further impurities and to provide a clean, flat surface for subsequent epitaxial layer growth. The final stage of preparation involves growing a semi-insulating buffer layer (11) on the substrate to isolate the device epitaxial layers (12 to 16) from the substrate.
CA002193098A 1994-06-29 1995-06-29 Preparation of semiconductor substrates Expired - Fee Related CA2193098C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP94304754.8 1994-06-29
EP94304754 1994-06-29
PCT/GB1995/001541 WO1996000979A1 (en) 1994-06-29 1995-06-29 Preparation of semiconductor substrates

Publications (2)

Publication Number Publication Date
CA2193098A1 true CA2193098A1 (en) 1996-01-11
CA2193098C CA2193098C (en) 2001-02-20

Family

ID=8217756

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002193098A Expired - Fee Related CA2193098C (en) 1994-06-29 1995-06-29 Preparation of semiconductor substrates

Country Status (6)

Country Link
EP (1) EP0767969A1 (en)
JP (1) JPH10504685A (en)
KR (1) KR970704246A (en)
CN (1) CN1092839C (en)
CA (1) CA2193098C (en)
WO (1) WO1996000979A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462361B1 (en) 1995-12-27 2002-10-08 Showa Denko K.K. GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure
TW522574B (en) * 1999-09-28 2003-03-01 Showa Denko Kk GaInP epitaxial stacking structure, a GaInP epitaxial stacking structure for FETs and a fabrication method thereof
US6956237B2 (en) 2002-12-28 2005-10-18 Lg.Philips Lcd Co., Ltd. Thin film transistor array substrate and method for manufacturing the same
CN100364063C (en) * 2004-06-21 2008-01-23 中国科学院半导体研究所 Chemical battery with porous indium phosphide, electrochemical corrosive system and method
CN106972058B (en) * 2016-12-15 2020-02-11 苏州能讯高能半导体有限公司 Semiconductor device and preparation method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01226796A (en) * 1988-03-04 1989-09-11 Sumitomo Electric Ind Ltd Treatment of indium-phosphorus substrate
CN1040401A (en) * 1989-04-14 1990-03-14 吉林大学 The heterogeneous vapor phase epitaxy technique of gallium arsenide/indium phosphide
JPH03161922A (en) * 1989-11-20 1991-07-11 Nec Corp Hetero-epitaxial growth of group iii-v compound semiconductor on dissimilar substrate
CN1053146A (en) * 1991-02-04 1991-07-17 中国科学院西安光学精密机械研究所 Mixing on the gallium arsenide substrate and matter extension

Also Published As

Publication number Publication date
EP0767969A1 (en) 1997-04-16
CA2193098C (en) 2001-02-20
KR970704246A (en) 1997-08-09
WO1996000979A1 (en) 1996-01-11
CN1092839C (en) 2002-10-16
CN1155353A (en) 1997-07-23
JPH10504685A (en) 1998-05-06

Similar Documents

Publication Publication Date Title
EP0301463A3 (en) Thin film silicon semiconductor device and process for producing it
CA2075020A1 (en) Method for preparing semiconductor member
EP0993048A3 (en) Nitride semiconductor device and its manufacturing method
EP1054442A3 (en) Method for growing epitaxial group III nitride compound semiconductors on silicon
EP0352471A3 (en) Method of planarising semiconductor devices
DE69432784D1 (en) Method of manufacturing a semiconductor substrate
CA2107174A1 (en) Epitaxial Magnesium Oxide as a Buffer Layer on (111) Tetrahedral Semiconductors
WO2005034208A3 (en) METHOD TO REDUCE STACKING FAULT NUCLEATION SITES AND REDUCE Vf DRIFT IN BIPOLAR DEVICES
EP0955681A3 (en) Optical semiconductor device and method of fabricating the same
WO2002001608A3 (en) METHOD FOR ACHIEVING IMPROVED EPITAXY QUALITY (SURFACE TEXTURE AND DEFECT DENSITY) ON FREE-STANDING (ALUMINUM, INDIUM, GALLIUM) NITRIDE ((Al,In,Ga)N) SUBSTRATES FOR OPTO-ELECTRONIC AND ELECTRONIC DEVICES
CA2392041A1 (en) Pendeoepitaxial growth of gallium nitride layers on sapphire substrates
EP0969505A3 (en) SOI substrate
MY113920A (en) Process for producing semiconductor substrate
EP0392480A3 (en) Method of manufacturing a semiconductor integrated circuit device
WO2003094218A3 (en) Method of growing monocrystalline oxide having a semiconductor device thereon
EP0866493A3 (en) Semiconductor substrate having compound semiconductor layer, process for its production, and electronic device fabricated on semiconductor substrate
CA2015891A1 (en) Method for forming variable width isolation structures
CA2193098A1 (en) Preparation of Semiconductor Substrates
EP0749154A3 (en) Method of fabricating a III-V compound semiconductor layer
CA2135500A1 (en) Method for Forming a Step on a Deposition Surface of a Substrate for a Superconducting Device Utilizing an Oxide Superconductor
EP0723039A3 (en) Compound semiconductor substrate and process of producing same
WO2002045140A3 (en) Semiconductor structures having a compliant substrate
EP1233445A3 (en) Process of manufacturing a semiconductor device
EP0631299A4 (en) Semiconductor expitaxial substrate.
TW364167B (en) A method relating to the manufacture of semiconductor devices

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed