KR970704246A - Method for preparing a semiconductor substrate and semiconductor device according to the method - Google Patents

Method for preparing a semiconductor substrate and semiconductor device according to the method Download PDF

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KR970704246A
KR970704246A KR1019960707298A KR19960707298A KR970704246A KR 970704246 A KR970704246 A KR 970704246A KR 1019960707298 A KR1019960707298 A KR 1019960707298A KR 19960707298 A KR19960707298 A KR 19960707298A KR 970704246 A KR970704246 A KR 970704246A
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폴 찰스 스퍼던스
마크 앤드류 솔터
마이클 존 할로
데이비드 존 뉴슨
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로버츠 사이먼 크리스토퍼
브리티쉬 텔리커뮤니케이션즈 퍼블릭 리미티드 캄파니
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Abstract

인화인듐 반도체 기판(10)은 반도체 디바이스(5)를 형성하는 에피택셜 층(12 내지 16)의 후속 성장을 위해 준비된다. 준비시에 상기 기판(10)은 기판으로부터의 확산에 의한 불순물 원자의 표면 누적 경향을 증진시키고 기판 표면으로부터 불순물 원자를 제거하기 위하여 먼저 어닐링된다. 상기 기판(10)은 불순물을 더 제거하고 후속 에피택셜층 성장을 위해 청정하고 평탄한 표면을 제공하기 위하여 표면 에칭된다. 준비의 최종 단계는 상기 기판과 에피택셜 층(12 내지 16)을 절연하기 위하여 기판상에 반절연 버퍼층(11)을 성장시키는 것과 관련된다.Indium phosphide semiconductor substrate 10 is prepared for subsequent growth of epitaxial layers 12-16 forming semiconductor device 5. In preparation, the substrate 10 is first annealed to enhance the surface accumulation tendency of the impurity atoms by diffusion from the substrate and to remove the impurity atoms from the substrate surface. The substrate 10 is surface etched to further remove impurities and provide a clean and flat surface for subsequent epitaxial layer growth. The final step of preparation involves growing a semi-insulating buffer layer 11 on the substrate to insulate the substrate and epitaxial layers 12-16.

Description

반도체 기판의 준비방법 및 그 방법에 따른 반도체 디바이스Method for preparing a semiconductor substrate and semiconductor device according to the method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 전형적인 HFET의 구조Figure 1 shows the structure of a typical HFET

Claims (21)

에피택셜 층의 후속 성장을 위해 반도체 기판을 준비하는 방법에 있어서, (a)기판에 또는 기판상에 존재하는 불순물 원자의 농도를 감소시키기 위하여 상기 기판을 어닐링하는 스텝; 및 (b)전부 또는 일부가 금속 원자로 도핑된 반도체 재료를 포함하는 1 또는 2 이상의 버퍼층을 기판상에 성장시키는 스텝; 을 포함하는 것을 특징으로 하는 반도체 기판 준비 방법.CLAIMS 1. A method of preparing a semiconductor substrate for subsequent growth of an epitaxial layer, comprising: (a) annealing the substrate to reduce the concentration of impurity atoms present on or on the substrate; And (b) growing at least one buffer layer on the substrate, the semiconductor layer being partially or partially doped with a metal atom; Method of preparing a semiconductor substrate comprising a. 제 1 항에 있어서, 상기 기판은 인화인듐을 포함하는 것을 특징으로 하는 방법.The method of claim 1 wherein the substrate comprises indium phosphide. 제 2 항에 있어서, 상기 어닐링 스텝은 인화수소 분위기에서 수행되는 것을 특징으로 하는 방법.3. The method of claim 2 wherein the annealing step is performed in a hydrogen phosphide atmosphere. 제 1 항 내지 제 3 항 중 어느 한 항에 있어서, 적어도 하나의 버퍼 층은 철이 도핑된 반도체 재료를 포함하는 것을 특징으로 하는 방법.The method of claim 1, wherein the at least one buffer layer comprises a semiconductor material doped with iron. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서, 적어도 하나의 버퍼층은 철이 도핑된 InP를 포함하는 것을 특징으로 하는 방법.The method of claim 1, wherein the at least one buffer layer comprises InP doped with iron. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서, 적어도 하나의 버퍼층은 철이 도핑된 AlInAs를 포함하는 것을 특징으로 하는 방법.The method of claim 1, wherein the at least one buffer layer comprises AlInAs doped with iron. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서, 2 이상의 버퍼층은 적어도 하나의 버퍼층이 철이 도핑된 InP를 포함하고, 적어도 하나이 버퍼층이 철이 도핑된 AlInAs을 포함하는 층으로 성장되는 것을 특징으로 하는 방법.5. The method of claim 1, wherein the at least two buffer layers comprise at least one buffer layer comprising iron-doped InP and at least one buffer layer comprising iron-doped AlInAs. Way. 제 4 항 내지 제 7 항 중 어느 한 항에 있어서, 상기 철 도핑 레벨은 1016내지 1017cm-3차수인 것을 특징으로 하는 방법.8. The method of any of claims 4 to 7, wherein the iron doping level is on the order of 1016 to 1017 cm -3 . 제 1 항 내지 제 8 항 중 어느 한 항에 있어서, 표면의 불순물을 제거하기 위하여 기판 표면을 에칭 하는 스텝을 더 포함하고, 상기 에칭 스텝은 상기 어닐링 스텝 이후 버퍼층 성장 스텝 이전에 수행되는 것을 특징으로 하는 방법.9. The method of any one of claims 1 to 8, further comprising etching a substrate surface to remove impurities from the surface, wherein the etching step is performed after the annealing step and before the buffer layer growth step. How to. 제 2 항을 인용하는 제 9항에 있어서, 상기 에칭 스텝은 3염화인을 포함하는 분위기에서 기판을 가열하는 것을 포함하는 것을 특징으로 하는 방법.10. The method of claim 9, wherein said etching step comprises heating the substrate in an atmosphere comprising phosphorus trichloride. 제 10 항에 있어서, 상기 분위기는 고순도의 수소를 더 포함하는 것을 특징으로 하는 방법.The method of claim 10 wherein the atmosphere further comprises high purity hydrogen. 기판상에 반도체 디바이스를 제조하는 방법에 있어서, 상기 기판은 제 1 항 내지 제 11 항 중 어느 한항에 따라 준비되는 것을 특징으로 하는 방법.12. A method of manufacturing a semiconductor device on a substrate, wherein the substrate is prepared according to any one of the preceding claims. 기판 및 기판상에 증착된 다수의 에피택셜 디바이스 층을 포함하고, 상기 기판은 제 1 항 내지 12 항 중 어느 한항에 따라 준비된 기판인 것을 특징으로 하는 방법.13. A method comprising a substrate and a plurality of epitaxial device layers deposited on the substrate, wherein the substrate is a substrate prepared according to any of the preceding claims. 제 1 항에 따라 준비된 헤테로 접합 전계효과 트랜지스터에 있어서, 철이 도핑된 AlInAs를 포함하는 제 1 버퍼층, 철이 도핑된 InP를 포함하는 제 2 버퍼층 및 비도핑 InP를 포함하는 덧씌워진 제 3 버퍼층을 포함하는 것을 특징으로 하는 헤테로 접합 전계효과 트랜지스터.16. A heterojunction field effect transistor prepared according to claim 1, comprising: a first buffer layer comprising iron doped AlInAs, a second buffer layer comprising iron doped InP, and an overlaid third buffer layer comprising undoped InP. Heterojunction field effect transistor, characterized in that. 제 1 항에 따라 준비된 고전자이동도 트랜지스터에 있어서, 철이 도핑된 AlInAs를 포함하는 제 1 버퍼층, 철이 도핑된 InP를 포함하는 제 2 버퍼층 및 비도핑 InP를 포함하는 덧씌워진 제 3 버퍼층을 포함하는 것을 특징으로 하는 고전자이동도 트랜지스터.A high electron mobility transistor prepared according to claim 1, comprising: a first buffer layer comprising iron-doped AlInAs, a second buffer layer comprising iron-doped InP, and an overlaid third buffer layer comprising undoped InP. A high electron mobility transistor, characterized in that. 광전자 집적회로에 있어서, 제 1 항 내지 제 12 항 중 어느 한 항에 따라 준비된 적어도 하나의 반도체 광소자를 포함하는 것을 특징으로 하는 광전자 집적회로.An optoelectronic integrated circuit, comprising: at least one semiconductor optical element prepared according to any one of claims 1 to 12. 반도체 디바이스의 후속 제조를 위하여 반도체 기판을 준비하는 방법에 있어서, 어닐링 공정에 의하여 기판에 또는 기판상에 존재하는 불순물 원자의 농도를 감소시키는 스텝 ; 및 상기 기판상에 1 또는 2 이상의 버퍼층을 제공함으로써 후속 디바이스 층과 반도체 기판을 실질적으로 절연하는 스텝을 포함하고, 모든 버퍼층 또는 적어도 1 이상의 버퍼층은 상기 반도체 기판과 상기 후속 디바이스 층간의 도전을 감소시키기 위하여 캐리어 트랩을 제공하는 것을 특징으로 하는 방법.CLAIMS 1. A method of preparing a semiconductor substrate for subsequent manufacture of a semiconductor device, comprising the steps of: reducing the concentration of impurity atoms present on or on a substrate by an annealing process; And substantially insulating the subsequent device layer and the semiconductor substrate by providing one or more buffer layers on the substrate, wherein all buffer layers or at least one buffer layer reduce the conductivity between the semiconductor substrate and the subsequent device layer. Providing a carrier trap. 제 17 항에 있어서, 적어도 하나의 버퍼층은 Ⅲ/Ⅳ비가 실질적으로 전기적 중성 재료를 제공하도록 조정된 Ⅲ/Ⅳ 반도체를 포함하는 것을 특징으로 하는 방법.18. The method of claim 17, wherein the at least one buffer layer comprises a III / IV semiconductor whose III / IV ratio is adapted to provide an electrically neutral material. 제 17 항에 있어서, 적어도 하나의 버퍼층은, 비도핑시 n-타입 또는 p-타입 특성을 나타내고, 캐리어 트랩을 공급하는 전기적으로 활성인 원자로 도핑되는 반도체 재료를 포함하는 것을 특징으로 하는 방법.18. The method of claim 17, wherein the at least one buffer layer comprises n-type or p-type characteristics when undoped and comprises a semiconductor material doped with electrically active atoms that supply a carrier trap. 제 19 항에 있어서, 상기 반도체 재료는, 비도핑시 n-타입 양상을 나타내고, 상기 전기적으로 중성인 원자는 철원자인 것을 특징으로 하는 방법.20. The method of claim 19, wherein the semiconductor material exhibits an n-type aspect upon undoping and wherein the electrically neutral atom is an iron atom. 제 19 항에 있어서, 상기 반도체 재료는, 비도핑시 p-타입 양상을 나타내고, 상기 전기적으로 활성인 원자는 크롬원자인 것을 특징으로 하는 방법.20. The method of claim 19, wherein the semiconductor material exhibits a p-type aspect when undoped, and wherein the electrically active atom is a chromium atom.
KR1019960707298A 1994-06-29 1995-06-29 Method for preparing a semiconductor substrate and semiconductor device according to the method KR970704246A (en)

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TW522574B (en) * 1999-09-28 2003-03-01 Showa Denko Kk GaInP epitaxial stacking structure, a GaInP epitaxial stacking structure for FETs and a fabrication method thereof
US6956237B2 (en) 2002-12-28 2005-10-18 Lg.Philips Lcd Co., Ltd. Thin film transistor array substrate and method for manufacturing the same
CN100364063C (en) * 2004-06-21 2008-01-23 中国科学院半导体研究所 Chemical battery with porous indium phosphide, electrochemical corrosive system and method
CN106972058B (en) * 2016-12-15 2020-02-11 苏州能讯高能半导体有限公司 Semiconductor device and preparation method thereof

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JPH10504685A (en) 1998-05-06
CN1155353A (en) 1997-07-23
CA2193098A1 (en) 1996-01-11
CA2193098C (en) 2001-02-20
WO1996000979A1 (en) 1996-01-11

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