CA2122880C - Crossbar switch for multi-processor system - Google Patents

Crossbar switch for multi-processor system

Info

Publication number
CA2122880C
CA2122880C CA002122880A CA2122880A CA2122880C CA 2122880 C CA2122880 C CA 2122880C CA 002122880 A CA002122880 A CA 002122880A CA 2122880 A CA2122880 A CA 2122880A CA 2122880 C CA2122880 C CA 2122880C
Authority
CA
Canada
Prior art keywords
output
input
memory
memory access
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002122880A
Other languages
English (en)
French (fr)
Other versions
CA2122880A1 (en
Inventor
Vinod Sharma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CA2122880A1 publication Critical patent/CA2122880A1/en
Application granted granted Critical
Publication of CA2122880C publication Critical patent/CA2122880C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478Provisions for broadband connections
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356Indirect interconnection networks
    • G06F15/17368Indirect interconnection networks non hierarchical topologies
    • G06F15/17375One dimensional, e.g. linear array, ring
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/25Routing or path finding in a switch fabric
    • H04L49/253Routing or path finding in a switch fabric using establishment or release of connections between ports
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Packet switching elements characterised by the switching fabric construction
    • H04L49/101Packet switching elements characterised by the switching fabric construction using crossbar or matrix
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/30Peripheral units, e.g. input or output ports
    • H04L49/3018Input queuing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/40Constructional details, e.g. power supply, mechanical construction or backplane
CA002122880A 1993-05-06 1994-05-04 Crossbar switch for multi-processor system Expired - Fee Related CA2122880C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5105226A JPH06314264A (ja) 1993-05-06 1993-05-06 セルフ・ルーティング・クロスバー・スイッチ
JP105226/1993 1993-05-06

Publications (2)

Publication Number Publication Date
CA2122880A1 CA2122880A1 (en) 1994-11-07
CA2122880C true CA2122880C (en) 1999-07-27

Family

ID=14401757

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002122880A Expired - Fee Related CA2122880C (en) 1993-05-06 1994-05-04 Crossbar switch for multi-processor system

Country Status (5)

Country Link
US (1) US5559970A (ja)
EP (1) EP0623880B1 (ja)
JP (1) JPH06314264A (ja)
CA (1) CA2122880C (ja)
DE (1) DE69425605T2 (ja)

Families Citing this family (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3452929B2 (ja) * 1993-09-27 2003-10-06 株式会社エヌ・ティ・ティ・ドコモ マルチプロセッサ
US6425881B1 (en) * 1994-10-05 2002-07-30 Nitrosystems, Inc. Therapeutic mixture useful in inhibiting lesion formation after vascular injury
US5761455A (en) * 1995-02-06 1998-06-02 Cpu Technology, Inc. Dynamic bus reconfiguration logic
JP2878160B2 (ja) * 1995-08-29 1999-04-05 甲府日本電気株式会社 競合調停装置
US6081873A (en) * 1997-06-25 2000-06-27 Sun Microsystems, Inc. In-line bank conflict detection and resolution in a multi-ported non-blocking cache
JP3893625B2 (ja) * 1997-10-21 2007-03-14 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 信号処理装置及び信号処理装置におけるプロセッサ間の接続を計画する方法
US6052760A (en) * 1997-11-05 2000-04-18 Unisys Corporation Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks
US6092156A (en) * 1997-11-05 2000-07-18 Unisys Corporation System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations
US6014709A (en) * 1997-11-05 2000-01-11 Unisys Corporation Message flow protocol for avoiding deadlocks
US6643746B1 (en) * 1997-12-24 2003-11-04 Creative Technology Ltd. Optimal multi-channel memory controller system
US6415364B1 (en) * 1997-12-31 2002-07-02 Unisys Corporation High-speed memory storage unit for a multiprocessor system having integrated directory and data storage subsystems
US6125429A (en) * 1998-03-12 2000-09-26 Compaq Computer Corporation Cache memory exchange optimized memory organization for a computer system
US6314501B1 (en) 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
US6473827B2 (en) * 1998-12-22 2002-10-29 Ncr Corporation Distributed multi-fabric interconnect
US6480941B1 (en) * 1999-02-23 2002-11-12 International Business Machines Corporation Secure partitioning of shared memory based multiprocessor system
US6597692B1 (en) * 1999-04-21 2003-07-22 Hewlett-Packard Development, L.P. Scalable, re-configurable crossbar switch architecture for multi-processor system interconnection networks
US6425043B1 (en) * 1999-07-13 2002-07-23 Micron Technology, Inc. Method for providing fast memory decode using a bank conflict table
US6425044B1 (en) * 1999-07-13 2002-07-23 Micron Technology, Inc. Apparatus for providing fast memory decode using a bank conflict table
US6404660B1 (en) * 1999-12-23 2002-06-11 Rambus, Inc. Semiconductor package with a controlled impedance bus and method of forming same
US20010052053A1 (en) * 2000-02-08 2001-12-13 Mario Nemirovsky Stream processing unit for a multi-streaming processor
US7502876B1 (en) 2000-06-23 2009-03-10 Mips Technologies, Inc. Background memory manager that determines if data structures fits in memory with memory state transactions map
US7076630B2 (en) * 2000-02-08 2006-07-11 Mips Tech Inc Method and apparatus for allocating and de-allocating consecutive blocks of memory in background memo management
US7649901B2 (en) * 2000-02-08 2010-01-19 Mips Technologies, Inc. Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing
US7058065B2 (en) * 2000-02-08 2006-06-06 Mips Tech Inc Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing
US7032226B1 (en) 2000-06-30 2006-04-18 Mips Technologies, Inc. Methods and apparatus for managing a buffer of events in the background
US7058064B2 (en) * 2000-02-08 2006-06-06 Mips Technologies, Inc. Queueing system for processors in packet routing operations
US7082552B2 (en) * 2000-02-08 2006-07-25 Mips Tech Inc Functional validation of a packet management unit
US7065096B2 (en) 2000-06-23 2006-06-20 Mips Technologies, Inc. Method for allocating memory space for limited packet head and/or tail growth
US7042887B2 (en) 2000-02-08 2006-05-09 Mips Technologies, Inc. Method and apparatus for non-speculative pre-fetch operation in data packet processing
US7155516B2 (en) * 2000-02-08 2006-12-26 Mips Technologies, Inc. Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
US7139901B2 (en) * 2000-02-08 2006-11-21 Mips Technologies, Inc. Extended instruction set for packet processing applications
US7165257B2 (en) * 2000-02-08 2007-01-16 Mips Technologies, Inc. Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
WO2001069411A2 (en) 2000-03-10 2001-09-20 Arc International Plc Memory interface and method of interfacing between functional entities
GB0008195D0 (en) 2000-04-05 2000-05-24 Power X Limited Data switching arbitration arrangements
AU5497401A (en) 2000-05-18 2001-11-26 Power X Limited Apparatus and method for resource arbitration
US6889304B2 (en) 2001-02-28 2005-05-03 Rambus Inc. Memory device supporting a dynamically configurable core organization
US7610447B2 (en) * 2001-02-28 2009-10-27 Rambus Inc. Upgradable memory system with reconfigurable interconnect
US7500075B1 (en) 2001-04-17 2009-03-03 Rambus Inc. Mechanism for enabling full data bus utilization without increasing data granularity
US6925520B2 (en) * 2001-05-31 2005-08-02 Sun Microsystems, Inc. Self-optimizing crossbar switch
US6825841B2 (en) * 2001-09-07 2004-11-30 Rambus Inc. Granularity memory column access
US7376811B2 (en) * 2001-11-06 2008-05-20 Netxen, Inc. Method and apparatus for performing computations and operations on data using data steering
US6865639B2 (en) * 2001-12-19 2005-03-08 Northrop Grumman Corporation Scalable self-routing superconductor switch
US7047374B2 (en) * 2002-02-25 2006-05-16 Intel Corporation Memory read/write reordering
WO2003100549A2 (en) 2002-05-24 2003-12-04 Koninklijke Philips Electronics N.V. Pseudo multiport data memory has stall facility
WO2003100618A2 (en) 2002-05-24 2003-12-04 Koninklijke Philips Electronics N.V. Programmed access latency in mock multiport memory
US7099983B2 (en) * 2002-11-25 2006-08-29 Lsi Logic Corporation Multi-core communications module, data communications system incorporating a multi-core communications module, and data communications process
US6996785B1 (en) 2003-04-25 2006-02-07 Universal Network Machines, Inc . On-chip packet-based interconnections using repeaters/routers
EP1473637A1 (de) * 2003-04-30 2004-11-03 Siemens Aktiengesellschaft Einrichtung sowie Verfahren zur Kopplung von Steuereinheiten mit gemeinsamen Speichereinheiten
US8250295B2 (en) 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
US7007128B2 (en) * 2004-01-07 2006-02-28 International Business Machines Corporation Multiprocessor data processing system having a data routing mechanism regulated through control communication
US7308558B2 (en) * 2004-01-07 2007-12-11 International Business Machines Corporation Multiprocessor data processing system having scalable data interconnect and data routing mechanism
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
JP2006039677A (ja) * 2004-07-22 2006-02-09 Fujitsu Ltd クロスバ
US8190808B2 (en) * 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
US7254075B2 (en) * 2004-09-30 2007-08-07 Rambus Inc. Integrated circuit memory system having dynamic memory bank count and page size
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US7600023B2 (en) * 2004-11-05 2009-10-06 Hewlett-Packard Development Company, L.P. Systems and methods of balancing crossbar bandwidth
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
KR100594967B1 (ko) 2004-11-29 2006-06-30 한국과학기술원 크로스바 스위치
JP4453915B2 (ja) * 2005-03-18 2010-04-21 富士通株式会社 クロスバー装置、制御方法及びプログラム
US20060248305A1 (en) * 2005-04-13 2006-11-02 Wayne Fang Memory device having width-dependent output latency
US8560795B2 (en) * 2005-06-30 2013-10-15 Imec Memory arrangement for multi-processor systems including a memory queue
EP2317446A1 (en) * 2005-06-30 2011-05-04 Imec A memory arrangement for multi-processor systems
US20070124554A1 (en) * 2005-10-28 2007-05-31 Honeywell International Inc. Global memory for a rapidio network
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
KR101388134B1 (ko) * 2007-10-01 2014-04-23 삼성전자주식회사 뱅크 충돌 방지 장치 및 방법
US8127049B1 (en) 2008-03-12 2012-02-28 Matrox Graphics Inc. Input/output pin allocation for data streams of variable widths
US8154901B1 (en) * 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
FR2946441A1 (fr) * 2009-06-08 2010-12-10 Commissariat Energie Atomique Reseau d'interconnexions a sous-reseaux dynamiques.
US8306042B1 (en) * 2009-06-19 2012-11-06 Google Inc. Class-based deterministic packet routing
JP5704012B2 (ja) * 2011-08-01 2015-04-22 富士通セミコンダクター株式会社 プロセッサ、及びプロセッサの制御方法
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US9558143B2 (en) 2014-05-09 2017-01-31 Micron Technology, Inc. Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device
WO2017019095A1 (en) 2015-07-30 2017-02-02 Hewlett Packard Enterprise Development Lp Interleaved access of memory
KR101923661B1 (ko) 2016-04-04 2018-11-29 주식회사 맴레이 플래시 기반 가속기 및 이를 포함하는 컴퓨팅 디바이스
US10162781B2 (en) 2016-06-01 2018-12-25 Micron Technology, Inc. Logic component switch
US10346347B2 (en) 2016-10-03 2019-07-09 The Regents Of The University Of Michigan Field-programmable crossbar array for reconfigurable computing
US10171084B2 (en) 2017-04-24 2019-01-01 The Regents Of The University Of Michigan Sparse coding with Memristor networks
US10943652B2 (en) 2018-05-22 2021-03-09 The Regents Of The University Of Michigan Memory processing unit
CN112526407B (zh) * 2020-11-24 2024-03-19 国网新疆电力有限公司信息通信公司 电力数字配线架2m端口连接装置及端口测试方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4745545A (en) * 1985-06-28 1988-05-17 Cray Research, Inc. Memory reference control in a multiprocessor
EP0365745A3 (en) * 1988-10-28 1990-12-27 International Business Machines Corporation A method for detecting and avoiding erroneous decombining in combining networks for parallel computing systems
US5202970A (en) * 1989-02-07 1993-04-13 Cray Research, Inc. Method for sharing memory in a multiprocessor system
US5197130A (en) * 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
US5239629A (en) * 1989-12-29 1993-08-24 Supercomputer Systems Limited Partnership Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system
US5276838A (en) * 1991-03-04 1994-01-04 International Business Machines Corporation Dynamically repositioned memory bank queues

Also Published As

Publication number Publication date
EP0623880A2 (en) 1994-11-09
DE69425605D1 (de) 2000-09-28
JPH06314264A (ja) 1994-11-08
DE69425605T2 (de) 2001-04-19
EP0623880A3 (en) 1995-11-02
US5559970A (en) 1996-09-24
CA2122880A1 (en) 1994-11-07
EP0623880B1 (en) 2000-08-23

Similar Documents

Publication Publication Date Title
CA2122880C (en) Crossbar switch for multi-processor system
KR900006793B1 (ko) 패킷 스위치 다중 대기행렬 NxM 스위치 노오드 및 처리 방법
KR900006791B1 (ko) 패킷 스위치식 다중포트 메모리 n×m 스위치 노드 및 처리 방법
US5152000A (en) Array communications arrangement for parallel processor
US7009964B2 (en) Rotator switch data path structures
US5123109A (en) Parallel processor including a processor array with plural data transfer arrangements including (1) a global router and (2) a proximate-neighbor transfer system
US5440523A (en) Multiple-port shared memory interface and associated method
EP0132926B1 (en) Parallel processor
US5212773A (en) Wormhole communications arrangement for massively parallel processor
US4709327A (en) Parallel processor/memory circuit
US5008815A (en) Parallel processor
US4598400A (en) Method and apparatus for routing message packets
US5229991A (en) Packet switch with broadcasting capability for atm networks
US5146608A (en) Parallel processor array system controlled in response to composition status signal
EP0492025B1 (en) High-speed multi-port FIFO buffer circuit
US5151996A (en) Multi-dimensional message transfer router
US4276611A (en) Device for the control of data flows
JP2679994B2 (ja) ベクトル処理装置
McMillen et al. Performance and implementation of 4 x 4 switching nodes in an interconnection network for PASM
Rana A control algorithm for 3-stage non-blocking networks
JP2882304B2 (ja) マルチプロセッサシステム
Kumar Performance improvement in single-stage and multiple-stage shuffle-exchange networks
Lee et al. New self-routing permutation networks
KR100317123B1 (ko) 선형 시스톨릭 라운드로빈 스케줄러 및 그의 스케줄링방법
JP2731738B2 (ja) マルチプロセッサシステム

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed