CA2080630A1 - Logique de controle d'arbitrage pour ordinateur a deux bus - Google Patents

Logique de controle d'arbitrage pour ordinateur a deux bus

Info

Publication number
CA2080630A1
CA2080630A1 CA2080630A CA2080630A CA2080630A1 CA 2080630 A1 CA2080630 A1 CA 2080630A1 CA 2080630 A CA2080630 A CA 2080630A CA 2080630 A CA2080630 A CA 2080630A CA 2080630 A1 CA2080630 A1 CA 2080630A1
Authority
CA
Canada
Prior art keywords
input
bus
arbitration
output
output devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2080630A
Other languages
English (en)
Other versions
CA2080630C (fr
Inventor
Nader Amini
Bechara Fouad Boury
Richard Louis Horne
Terence Joseph Lohman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2080630A1 publication Critical patent/CA2080630A1/fr
Application granted granted Critical
Publication of CA2080630C publication Critical patent/CA2080630C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
    • G06F13/225—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
CA002080630A 1992-01-02 1992-10-15 Logique de controle d'arbitrage pour ordinateur a deux bus Expired - Fee Related CA2080630C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/816,116 US5265211A (en) 1992-01-02 1992-01-02 Arbitration control logic for computer system having dual bus architecture
US07/816,116 1992-01-02

Publications (2)

Publication Number Publication Date
CA2080630A1 true CA2080630A1 (fr) 1993-07-03
CA2080630C CA2080630C (fr) 1996-10-22

Family

ID=25219732

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002080630A Expired - Fee Related CA2080630C (fr) 1992-01-02 1992-10-15 Logique de controle d'arbitrage pour ordinateur a deux bus

Country Status (10)

Country Link
US (1) US5265211A (fr)
EP (1) EP0550223A3 (fr)
JP (1) JP2642027B2 (fr)
KR (1) KR960012660B1 (fr)
CN (1) CN1029167C (fr)
AU (1) AU651747B2 (fr)
CA (1) CA2080630C (fr)
NZ (1) NZ245345A (fr)
SG (1) SG42882A1 (fr)
TW (1) TW288123B (fr)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768548A (en) * 1992-04-15 1998-06-16 Intel Corporation Bus bridge for responding to received first write command by storing data and for responding to received second write command by transferring the stored data
US5467295A (en) * 1992-04-30 1995-11-14 Intel Corporation Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit
JP2531903B2 (ja) * 1992-06-22 1996-09-04 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュ―タ・システムおよびシステム拡張装置
US5450547A (en) * 1992-10-01 1995-09-12 Xerox Corporation Bus interface using pending channel information stored in single circular queue for controlling channels of data transfer within multiple FIFO devices
US5335326A (en) * 1992-10-01 1994-08-02 Xerox Corporation Multichannel FIFO device channel sequencer
US5495585A (en) * 1992-10-16 1996-02-27 Unisys Corporation Programmable timing logic system for dual bus interface
TW276312B (fr) * 1992-10-20 1996-05-21 Cirrlis Logic Inc
US5535414A (en) * 1992-11-13 1996-07-09 International Business Machines Corporation Secondary data transfer mechanism between coprocessor and memory in multi-processor computer system
US5799205A (en) * 1992-11-13 1998-08-25 Mannesmann Aktiengesellschaft Transfer system for data exchange using two active central processing units directly connected together parallel to serial system bus directly connecting CPUs to dispersed devices
EP0601715A1 (fr) * 1992-12-11 1994-06-15 National Semiconductor Corporation Bus de noyau CPV optimisé pour l'accès aux circuits de mémoire on-chip
US5386517A (en) * 1993-01-26 1995-01-31 Unisys Corporation Dual bus communication system connecting multiple processors to multiple I/O subsystems having a plurality of I/O devices with varying transfer speeds
CA2109043A1 (fr) * 1993-01-29 1994-07-30 Charles R. Moore Systeme et methode de transfert de donnees entre plusieurs bus
US5511224A (en) * 1993-02-18 1996-04-23 Unisys Corporation Configurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memories
US5528765A (en) * 1993-03-15 1996-06-18 R. C. Baker & Associates Ltd. SCSI bus extension system for controlling individual arbitration on interlinked SCSI bus segments
US5396602A (en) * 1993-05-28 1995-03-07 International Business Machines Corp. Arbitration logic for multiple bus computer system
US5450551A (en) * 1993-05-28 1995-09-12 International Business Machines Corporation System direct memory access (DMA) support logic for PCI based computer system
US5799161A (en) * 1993-06-25 1998-08-25 Intel Corporation Method and apparatus for concurrent data routing
US5708794A (en) * 1993-08-10 1998-01-13 Dell Usa, L.P. Multi-purpose usage of transaction backoff and bus architecture supporting same
US5771397A (en) * 1993-12-09 1998-06-23 Quantum Corporation SCSI disk drive disconnection/reconnection timing method for reducing bus utilization
US5666516A (en) * 1993-12-16 1997-09-09 International Business Machines Corporation Protected programmable memory cartridge having selective access circuitry
US5761450A (en) * 1994-02-24 1998-06-02 Intel Corporation Bus bridge circuit flushing buffer to a bus during one acquire/relinquish cycle by providing empty address indications
US5745732A (en) * 1994-11-15 1998-04-28 Cherukuri; Ravikrishna V. Computer system including system controller with a write buffer and plural read buffers for decoupled busses
US5623697A (en) * 1994-11-30 1997-04-22 International Business Machines Corporation Bridge between two buses of a computer system with a direct memory access controller having a high address extension and a high count extension
US5898857A (en) * 1994-12-13 1999-04-27 International Business Machines Corporation Method and system for interfacing an upgrade processor to a data processing system
US5603041A (en) * 1994-12-13 1997-02-11 International Business Machines Corporation Method and system for reading from a m-byte memory utilizing a processor having a n-byte data bus
US5625779A (en) * 1994-12-30 1997-04-29 Intel Corporation Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge
US6212589B1 (en) * 1995-01-27 2001-04-03 Intel Corporation System resource arbitration mechanism for a host bridge
US5687393A (en) * 1995-06-07 1997-11-11 International Business Machines Corporation System for controlling responses to requests over a data bus between a plurality of master controllers and a slave storage controller by inserting control characters
US5966715A (en) * 1995-12-29 1999-10-12 Csg Systems, Inc. Application and database security and integrity system and method
US5748968A (en) * 1996-01-05 1998-05-05 Cirrus Logic, Inc. Requesting device capable of canceling its memory access requests upon detecting other specific requesting devices simultaneously asserting access requests
US5774744A (en) * 1996-04-08 1998-06-30 Vlsi Technology, Inc. System using DMA and descriptor for implementing peripheral device bus mastering via a universal serial bus controller or an infrared data association controller
US5845151A (en) * 1996-04-08 1998-12-01 Vlsi Technology, Inc. System using descriptor and having hardware state machine coupled to DMA for implementing peripheral device bus mastering via USB controller or IrDA controller
US5752260A (en) * 1996-04-29 1998-05-12 International Business Machines Corporation High-speed, multiple-port, interleaved cache with arbitration of multiple access addresses
US5897656A (en) * 1996-09-16 1999-04-27 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
US6049847A (en) * 1996-09-16 2000-04-11 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
US5930483A (en) * 1996-12-09 1999-07-27 International Business Machines Corporation Method and apparatus for communications control on a small computer system interface
US6442632B1 (en) 1997-09-05 2002-08-27 Intel Corporation System resource arbitration mechanism for a host bridge
US6205500B1 (en) * 1997-09-24 2001-03-20 Compaq Computer Corp. System and method for electrically isolating a device from higher voltage devices
US6393508B2 (en) * 1997-09-30 2002-05-21 Texas Instruments Incorporated Method and apparatus for multiple tier intelligent bus arbitration on a PCI to PCI bridge
US6430641B1 (en) * 1999-05-04 2002-08-06 International Business Machines Corporation Methods, arbiters, and computer program products that can improve the performance of a pipelined dual bus data processing system
US6567871B2 (en) * 1999-07-26 2003-05-20 Intel Corporation Method and apparatus for repeating (extending) transactions on a bus without clock delay
US6693914B1 (en) * 1999-10-01 2004-02-17 Stmicroelectronics, Inc. Arbitration mechanism for packet transmission
KR100442440B1 (ko) * 2001-08-28 2004-07-30 엘지전자 주식회사 프로그램 로직을 이용한 메모리 액세스 제어방법 및 장치
CN1322437C (zh) * 2003-10-24 2007-06-20 旺玖科技股份有限公司 用于供多主机存取储存媒体的多主机存取装置
US8422568B2 (en) 2004-01-28 2013-04-16 Rambus Inc. Communication channel calibration for drift conditions
US7095789B2 (en) 2004-01-28 2006-08-22 Rambus, Inc. Communication channel calibration for drift conditions
US7158536B2 (en) * 2004-01-28 2007-01-02 Rambus Inc. Adaptive-allocation of I/O bandwidth using a configurable interconnect topology
US7400670B2 (en) 2004-01-28 2008-07-15 Rambus, Inc. Periodic calibration for communication channels by drift tracking
US6961862B2 (en) * 2004-03-17 2005-11-01 Rambus, Inc. Drift tracking feedback for communication channels
KR101480801B1 (ko) 2013-05-08 2015-01-12 한국화학연구원 이산화탄소 개질반응용 모노리스 촉매, 이의 제조방법 및 이를 이용한 합성가스의 제조방법
CN106155951B (zh) * 2015-03-30 2024-01-12 上海黄浦船用仪器有限公司 一种双总线仲裁控制系统及其应用
US10387259B2 (en) * 2015-06-26 2019-08-20 Intel Corporation Instant restart in non volatile system memory computing systems with embedded programmable data checking
JP6513695B2 (ja) * 2015-10-01 2019-05-15 ルネサスエレクトロニクス株式会社 半導体装置
CN105260331B (zh) * 2015-10-09 2018-08-28 天津国芯科技有限公司 一种双总线内存控制器
AU2020202306A1 (en) * 2019-04-02 2020-10-22 The Raymond Corporation Systems and methods for an arbitration controller to arbitrate multiple automation requests on a material handling device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4281381A (en) * 1979-05-14 1981-07-28 Bell Telephone Laboratories, Incorporated Distributed first-come first-served bus allocation apparatus
US4766536A (en) * 1984-04-19 1988-08-23 Rational Computer bus apparatus with distributed arbitration
US4703420A (en) * 1985-02-28 1987-10-27 International Business Machines Corporation System for arbitrating use of I/O bus by co-processor and higher priority I/O units in which co-processor automatically request bus access in anticipation of need
US4982321A (en) * 1987-10-23 1991-01-01 Honeywell Inc. Dual bus system
US5003465A (en) * 1988-06-27 1991-03-26 International Business Machines Corp. Method and apparatus for increasing system throughput via an input/output bus and enhancing address capability of a computer system during DMA read/write operations between a common memory and an input/output device
US5003463A (en) * 1988-06-30 1991-03-26 Wang Laboratories, Inc. Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
JP2545936B2 (ja) * 1988-07-18 1996-10-23 日本電気株式会社 バスインターフェースユニット
EP0375900A3 (fr) * 1988-12-29 1991-09-18 International Business Machines Corporation Système ordinateur
US5204951A (en) * 1989-10-02 1993-04-20 International Business Machines Corporation Apparatus and method for improving the communication efficiency between a host processor and peripheral devices connected by an scsi bus

Also Published As

Publication number Publication date
CN1074049A (zh) 1993-07-07
KR930016885A (ko) 1993-08-30
AU651747B2 (en) 1994-07-28
CA2080630C (fr) 1996-10-22
KR960012660B1 (ko) 1996-09-23
JP2642027B2 (ja) 1997-08-20
US5265211A (en) 1993-11-23
JPH05242011A (ja) 1993-09-21
EP0550223A2 (fr) 1993-07-07
CN1029167C (zh) 1995-06-28
EP0550223A3 (en) 1993-09-01
TW288123B (fr) 1996-10-11
AU2979492A (en) 1993-07-08
NZ245345A (en) 1995-07-26
SG42882A1 (en) 1997-10-17

Similar Documents

Publication Publication Date Title
CA2080630A1 (fr) Logique de controle d'arbitrage pour ordinateur a deux bus
MY112381A (en) Arbitration control logic for computer system having dual bus architecture
US6014729A (en) Shared memory arbitration apparatus and method
MY109414A (en) Bus interface logic for computer system having dual bus architecture
US5555425A (en) Multi-master bus arbitration system in which the address and data lines of the bus may be separately granted to individual masters
EP0588472B1 (fr) Ordinateur personnel avec registres fifo au seuil programmable pour le transfert de données
US4602327A (en) Bus master capable of relinquishing bus on request and retrying bus cycle
US5119480A (en) Bus master interface circuit with transparent preemption of a data transfer operation
CA1129109A (fr) Appareil de traitement d'interruptions multiniveaux
CA2124031A1 (fr) Logique de soutien d'acces direct memoire pour ordinateur a cartes de circuit imprime
CA2118995A1 (fr) Logique d'arbitrage pour ordinateur a bus multiples
HK1019250A1 (en) Microprocessor architecture capable of supporting multiple heterogenous processors
JP3039557B2 (ja) 記憶装置
CA2060820A1 (fr) Acces direct memoire pour le transfert de donnees dans un dispositif d'entree-sortie
US5471639A (en) Apparatus for arbitrating for a high speed direct memory access bus
CA2067602A1 (fr) Ordinateur personnel a signalisation de controle de memoire anticipee
US5732226A (en) Apparatus for granting either a CPU data bus or a memory data bus or a memory data bus access to a PCI bus
JPH0227696B2 (ja) Johoshorisochi
US6813671B1 (en) Controller for hot swapping of extended I/O device to computer body
JPH09223103A (ja) 情報処理システム
JP2574821B2 (ja) ダイレクトメモリアクセス・コントローラ
EP0439594B1 (fr) Appareil pour connecter un bus de processeur principal connecte a un processeur principal a un bus peripherique connecte a plusieurs appareils perpheriques
EP0818008B1 (fr) Memoire ram dynamique faisant partie d'un systeme microprocesseur
JP2504528B2 (ja) 主記憶制御装置間バス制御方式
JPS6337418B2 (fr)

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed
MKLA Lapsed

Effective date: 20121015