CA2072516A1 - Method and devices for testing atm connections - Google Patents
Method and devices for testing atm connectionsInfo
- Publication number
- CA2072516A1 CA2072516A1 CA002072516A CA2072516A CA2072516A1 CA 2072516 A1 CA2072516 A1 CA 2072516A1 CA 002072516 A CA002072516 A CA 002072516A CA 2072516 A CA2072516 A CA 2072516A CA 2072516 A1 CA2072516 A1 CA 2072516A1
- Authority
- CA
- Canada
- Prior art keywords
- cell
- test
- connection
- activated
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
Abstract
- - J. VAN TETERING - F. DENISSEN
ABSTRACT
METHOD AND DEVICES FOR TESTING ATM
CONNECTIONS
The information part of the test cells has twice the same contents, including time indications, sequence number within a connection and connection number. The repetition of the contents occurs octet per octet in inverse form.
ABSTRACT
METHOD AND DEVICES FOR TESTING ATM
CONNECTIONS
The information part of the test cells has twice the same contents, including time indications, sequence number within a connection and connection number. The repetition of the contents occurs octet per octet in inverse form.
Description
2~5~ ~
- 1 - J. VAN TETERING - F. DENISSEN
METHQD AND DEVICES FOR TESTING ATM
CONNECTIONS
.
The present invention relates to a method for testing the characteristics of an ATM connection, to a test cell generator with devices for ganerating the data sequence of an ATM test cell and to an evaluation circuit for testing ATM test cells.
In ATM-systems errors of various kinds maY occur and must all be detected in whatever way. For instance, an error is certainly present when no bit or cell synchronisation can be performed. Also the absence of response to whatever questions should be recognized as an error. It is also known to include in the information part of an ATM cell an error protection code to detect transmission errors.
Not all kinds of errors can be detected. This is the case with errors which occur onlY spuriously, although such errors adversely affect the transmission quality of an ATM connection between two points of an ATM network.
A solution to this problem is siven by a method according to claim 1. This method is preferably performed by means of a test cell senerator according to claim 5 and of an evaluation circuit according to claim 11.
The basic idea of this solution is the realization of test connections with a sequence of test cells suitablY
built uP.
Preferred embodements are apparent from the subclaims. A suitably built up te5t cell ,~u5t as everY
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_ 1-2 .
ATM cell. comprises a cell header and an information part, tha information part accordin~ to the invention havins twice the same contents, ,amongst which a time indication, a connection number and a sequence number of the cell in a connection. The repetition of the contents happens in inverse form. Preferably each octet should be followed by its inverse.
In this way substant,ially all characteristics of an ATM connection can be tested. This method is also advantageous in that in the information part the numbers of zeroes and ones are,equal 50 that the parity is not affected. Al~o the method can be executed by simple means.
The above mentioned and other objects and features of the invention will become more apparent and the lS invention itself will be best understood by referrins to the followins description of an embodiment taken in conjunction with the accompany-ing drawings wherein :
Fig. 1 shows the structure of an ATM test cell according to the invention;
Fig. 2 represents a block diagram of a test cell generator according to the invention;
Fig. 3 shows a block diagram of an e~aluation circuit according to the invention.
In a schematic way the first line of Fig. 1 shows the structure of a complete ATM test cell. The cell begins with a header H comprising five octets or bytes. This cell header H is used in a known way to transfer the cell to a predetermined destination within an ATM network. The structure of this cell header is not characteristic for the invention and the cell header may be changed on purpose within the course of a connection. It can therefore not be included in the test. For the present invention it i5 al5o without importance which kind o~ connection to-be tested is concerned, i.e. if a connection between two points within an exchange is concerned or if a connection between two .
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distant points is tested or if a loop ~hich is built up and tested is concerned.
The header H ~or instance contains a pair of bits serving to distinguish test and maintenance cells from data cells ~ithin a connection, whereas the first octet MCT of the information part following the ~ell header H i5 used to distinguish test cells from maintenance cells. For MCT a predetermined code has to be reserved.
The follo~ing octet. MCT, rapresents the in~erse of the preceeding octet MCT. This inversion is performed in such a way that every but is inverted.
MCT and MCT are followed by 18 octets which alternately contain either only ones or zeroes. Each pair of such octets constitutes a flag FL These 18 octets have three purposes. Errors which maintain a connection continuously on zero or on one should be recognized. T~o types of ATM test cells should be distinguished from each other. namely a TYPE-l cell the data of ~hich are transmitted in a non-inverted ~ay and is followed by their inverse form and a TYPE-0 cell the data of which are inverted, the followins inverted octet then containing the non inverted data. Each pair of octets is finally also used to detect bit errors.
` Measurement data MD follo~ tltese 18 octets. Three different measurement data are transmitted, namely a time indication TS. a sequence number SN of the cell in the connection. and a connection number ID. These three measurement data are each time transmitted as 16-bit words.
For a TYPE-l cell TlC the transfer is performed in the order T1. Tl. T2. T2. etc. as represented in Fig. 1.
The time indication TS is used to take the variation in transfer time (delay time) into account. The sequence number SN is used to detect the disappearance or repetition of a cell. A faulty connection number ID indicates that a cell of another connection has erroneously appeared in this 5~
- 1 - J. VAN TETERING - F. DENISSEN
METHQD AND DEVICES FOR TESTING ATM
CONNECTIONS
.
The present invention relates to a method for testing the characteristics of an ATM connection, to a test cell generator with devices for ganerating the data sequence of an ATM test cell and to an evaluation circuit for testing ATM test cells.
In ATM-systems errors of various kinds maY occur and must all be detected in whatever way. For instance, an error is certainly present when no bit or cell synchronisation can be performed. Also the absence of response to whatever questions should be recognized as an error. It is also known to include in the information part of an ATM cell an error protection code to detect transmission errors.
Not all kinds of errors can be detected. This is the case with errors which occur onlY spuriously, although such errors adversely affect the transmission quality of an ATM connection between two points of an ATM network.
A solution to this problem is siven by a method according to claim 1. This method is preferably performed by means of a test cell senerator according to claim 5 and of an evaluation circuit according to claim 11.
The basic idea of this solution is the realization of test connections with a sequence of test cells suitablY
built uP.
Preferred embodements are apparent from the subclaims. A suitably built up te5t cell ,~u5t as everY
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, 2~ 6 - 2 - J. VAN TETERING - F. ~ENISSEN
_ 1-2 .
ATM cell. comprises a cell header and an information part, tha information part accordin~ to the invention havins twice the same contents, ,amongst which a time indication, a connection number and a sequence number of the cell in a connection. The repetition of the contents happens in inverse form. Preferably each octet should be followed by its inverse.
In this way substant,ially all characteristics of an ATM connection can be tested. This method is also advantageous in that in the information part the numbers of zeroes and ones are,equal 50 that the parity is not affected. Al~o the method can be executed by simple means.
The above mentioned and other objects and features of the invention will become more apparent and the lS invention itself will be best understood by referrins to the followins description of an embodiment taken in conjunction with the accompany-ing drawings wherein :
Fig. 1 shows the structure of an ATM test cell according to the invention;
Fig. 2 represents a block diagram of a test cell generator according to the invention;
Fig. 3 shows a block diagram of an e~aluation circuit according to the invention.
In a schematic way the first line of Fig. 1 shows the structure of a complete ATM test cell. The cell begins with a header H comprising five octets or bytes. This cell header H is used in a known way to transfer the cell to a predetermined destination within an ATM network. The structure of this cell header is not characteristic for the invention and the cell header may be changed on purpose within the course of a connection. It can therefore not be included in the test. For the present invention it i5 al5o without importance which kind o~ connection to-be tested is concerned, i.e. if a connection between two points within an exchange is concerned or if a connection between two .
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distant points is tested or if a loop ~hich is built up and tested is concerned.
The header H ~or instance contains a pair of bits serving to distinguish test and maintenance cells from data cells ~ithin a connection, whereas the first octet MCT of the information part following the ~ell header H i5 used to distinguish test cells from maintenance cells. For MCT a predetermined code has to be reserved.
The follo~ing octet. MCT, rapresents the in~erse of the preceeding octet MCT. This inversion is performed in such a way that every but is inverted.
MCT and MCT are followed by 18 octets which alternately contain either only ones or zeroes. Each pair of such octets constitutes a flag FL These 18 octets have three purposes. Errors which maintain a connection continuously on zero or on one should be recognized. T~o types of ATM test cells should be distinguished from each other. namely a TYPE-l cell the data of ~hich are transmitted in a non-inverted ~ay and is followed by their inverse form and a TYPE-0 cell the data of which are inverted, the followins inverted octet then containing the non inverted data. Each pair of octets is finally also used to detect bit errors.
` Measurement data MD follo~ tltese 18 octets. Three different measurement data are transmitted, namely a time indication TS. a sequence number SN of the cell in the connection. and a connection number ID. These three measurement data are each time transmitted as 16-bit words.
For a TYPE-l cell TlC the transfer is performed in the order T1. Tl. T2. T2. etc. as represented in Fig. 1.
The time indication TS is used to take the variation in transfer time (delay time) into account. The sequence number SN is used to detect the disappearance or repetition of a cell. A faulty connection number ID indicates that a cell of another connection has erroneously appeared in this 5~
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connection and that the cell header thus has been modi~ied erroneousl,y .
The rest of the test cell is campleted with octets which again alternately contain only ones or only zeroes.
By inverting octet per octet inside the whole information part. no part of the cell is left out of consideration.
Inside a cell errors could be produced resulting from a parallel processing with a 16-bit width. Therefore in a test connection tha tWQ kinds of test cells TYPE-1 and TYPE-0 are-used alternately and in predetermined or arbitrary order.
Fig. 2 shows an embodiment o~ a test cell QeneratOr by which the above described ATM cells maY be senerated.
The test cell generator TG includes a control circuit TCGC. a read and write mamory MEM, a connection number generator ID, a clock LT. a three-state bus TSB
having a width oP 8 bits. an inverter IN~ and an output register REG~
The clock circuit LT, the connection number generator ID and the memory MEM are provided with three-state outputs which are able to be activated via activation inputs ~El. OE2. OE3~with the help o~ the like named activation signals OEl. OE2. OE3. The leads of the three-state bus TSB are connected to the supply voltage VCC
via resistances R. The clock circuit LT and the connection number generator ID are provided with an invert`ing input SeUL via which and by means of a like named inversion signal SeUL an inversion from high value to low value data ~ytes and vice-versa may be realized. The clock circuit LT
30 i5 controlled by the cell clock cir~uit CCL. whilst the output register REG is controlled by the byte clock BCL.
The inverter INV may be switched between the non inverting - and the inverting condition by means of a signal INVC. The memory MEM may transmit data via the bus TSB as well as to the control circuit TCGC or receive data from this circuit.
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connection and that the cell header thus has been modi~ied erroneousl,y .
The rest of the test cell is campleted with octets which again alternately contain only ones or only zeroes.
By inverting octet per octet inside the whole information part. no part of the cell is left out of consideration.
Inside a cell errors could be produced resulting from a parallel processing with a 16-bit width. Therefore in a test connection tha tWQ kinds of test cells TYPE-1 and TYPE-0 are-used alternately and in predetermined or arbitrary order.
Fig. 2 shows an embodiment o~ a test cell QeneratOr by which the above described ATM cells maY be senerated.
The test cell generator TG includes a control circuit TCGC. a read and write mamory MEM, a connection number generator ID, a clock LT. a three-state bus TSB
having a width oP 8 bits. an inverter IN~ and an output register REG~
The clock circuit LT, the connection number generator ID and the memory MEM are provided with three-state outputs which are able to be activated via activation inputs ~El. OE2. OE3~with the help o~ the like named activation signals OEl. OE2. OE3. The leads of the three-state bus TSB are connected to the supply voltage VCC
via resistances R. The clock circuit LT and the connection number generator ID are provided with an invert`ing input SeUL via which and by means of a like named inversion signal SeUL an inversion from high value to low value data ~ytes and vice-versa may be realized. The clock circuit LT
30 i5 controlled by the cell clock cir~uit CCL. whilst the output register REG is controlled by the byte clock BCL.
The inverter INV may be switched between the non inverting - and the inverting condition by means of a signal INVC. The memory MEM may transmit data via the bus TSB as well as to the control circuit TCGC or receive data from this circuit.
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To this end an 8-bit wide bidirectional data cannection MDA
is provided between both circuits and between the control circuit TCGC and the memory MEM al50 a three bit wide address connection, a write lead M~ and a read lead MR are foreseen.
Next to the connections to the memory already mentioned the control circuit TCGC is also provided with outputs OEl, OE2, OE3 for the activating signals ~E1, OE2 and OE3 and for the activation of the three-state outputs, with an output SeUL for the like named inversion signal SeUL. with outputs CCL and BCL for the cell clack CCL and the byte clock BCL, and with the output INVC fnr the sisnal INVC controllins the inverter IN~.
The octets of the cell header H are generated bY the memory MEM and fed through the inverter INV without inversion. The two following octets, MCT and MCT, are generated by the memory MEM two times after each other in the non-inverse form and are fed throush the inverter nnce without inversion and once with inversion. The flags FL
are formed with the help of the resistances R when the three-state outputs are not activated, and then by alternate non-inversion and inversion in the inverter INV.
The time indication is provided by the clock circuit LT.
the sequence number i5 ~enerated by the memory MEM and the connection number is provided by the connection number generator ID. Hereby each time the hish value data byte is generated twice and the low value data byte is generated twice. and fed throush the inverter once without inversion and once with inversion. The sequence number stored in the memory MEM is resistered in the control circuit TCGC after each complete transmission. it is incremented therein by one and then reloaded in memory MEM.
The subsequent flags are obtained in the same way as the first flags.
The control circuit TCGC essentially operates in the ,,' :
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5~
To this end an 8-bit wide bidirectional data cannection MDA
is provided between both circuits and between the control circuit TCGC and the memory MEM al50 a three bit wide address connection, a write lead M~ and a read lead MR are foreseen.
Next to the connections to the memory already mentioned the control circuit TCGC is also provided with outputs OEl, OE2, OE3 for the activating signals ~E1, OE2 and OE3 and for the activation of the three-state outputs, with an output SeUL for the like named inversion signal SeUL. with outputs CCL and BCL for the cell clack CCL and the byte clock BCL, and with the output INVC fnr the sisnal INVC controllins the inverter IN~.
The octets of the cell header H are generated bY the memory MEM and fed through the inverter INV without inversion. The two following octets, MCT and MCT, are generated by the memory MEM two times after each other in the non-inverse form and are fed throush the inverter nnce without inversion and once with inversion. The flags FL
are formed with the help of the resistances R when the three-state outputs are not activated, and then by alternate non-inversion and inversion in the inverter INV.
The time indication is provided by the clock circuit LT.
the sequence number i5 ~enerated by the memory MEM and the connection number is provided by the connection number generator ID. Hereby each time the hish value data byte is generated twice and the low value data byte is generated twice. and fed throush the inverter once without inversion and once with inversion. The sequence number stored in the memory MEM is resistered in the control circuit TCGC after each complete transmission. it is incremented therein by one and then reloaded in memory MEM.
The subsequent flags are obtained in the same way as the first flags.
The control circuit TCGC essentially operates in the ,,' :
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.
same way as a known prosramming circuit. requiring a counter and a programme memory. To these circuits an adder circuit for incrementing the sequence number as well as known devices for providing the timing have to be added~
Fig. 3 shows a Possible embodement of an evaluation circuit EC for testing ATM test cells. This evaluation circuit EC includes a circuit ERRC for fault recognition, a circuit HIDC for e.g. cell header recngnition. a circuit TYPD for cell type recognition, a clock LCTI, a circuit SEQE for determining the sequence number. and a circuit DELC for determining a relative or absolut~ transfer time.
The fault recognition circuit ERRC investigates if octets occur in associated pairs which are mutually inverted. To this end a memory. an inverter and a comparison circuit are required for each of the eisht bits.
The errors occurr;ng within an ATM test cell are counted, the counter position of this counter constituting the signal ERR PAT. Further signals are provided: ERR SEQ when an error occurs in the sequence number; ERR TIME when an error occurs in the time indication. and ERR ID when an error occurs in the sequence number. The signals ERR PAT
and ERR ID are also transmitted to thè circuit ~or cell header recognition HIDC.
The so called cell header recognition circuit HIDC
compares the five bytes of the cell header of an incoming cell with the five bytes of a referencP cell. the header bytes each includins a pair of above mentioned bits.
hereafter called PT. which are activated when test or maintenance cells are concerned and which are not activated in the case of data cells. Hereby the output CELL REC is activated when :
- PT i5 activated and when not only the five bytes of the header unit also but also the MCT and MCT bytes are equal; or when - PT i5 not activated and the five bytes of the header are . ~ , ~ .
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equal.
~ hen now CELL REC is activated then the sequence number of the incoming cell i5 compared with that of the reference cell and the output CELL INS i5 thereby activated ~hen :
- these connection numbers are different and there are no errors in the connection number of the incomin~ cell;
- the last mentioned connection number is erroneous and the signal ERR PAT moreover exceeds a predetermined threshold.
The circuit for cell type recognition TYPD
distinsuishes bet~een cells of type TYPE-l and cells of TYPE-û and produces a signal TYPE indicating the cell type.
The circuit SEQE for determining the sequence number e~tracts the sequence number as a 16-bit signal SEQ NR in function of the signal TYPE.
The circuit DELC for determining the relative or absolute transfer time DERLC extracts the time indication TS from the cell in function of the signal TYPE, subtracts it from the local time LTI of the clock LCTI and produces at its output the difference as a 16-bit signal DL. When the clock circuit LT in the test cell generator T6 and the clock LCTI in the evaluation circuit are not runnins in synchronism the absolute transfer time cannot be obtained.
~owever. for a sequence of test calls the relative transfer timP differences may be obtained in this way and these transfer time differences are in general of greater importance than the absolute values of the transfer times.
By the above invention all means are provided for testing the characteristics of an ATM connection.
While the principles of th`e invention have been described abo~e in connection with specific apparatus, it is to be clearly understood that this description is made only by waY of example and not as a limitation on the scope of the invention.
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same way as a known prosramming circuit. requiring a counter and a programme memory. To these circuits an adder circuit for incrementing the sequence number as well as known devices for providing the timing have to be added~
Fig. 3 shows a Possible embodement of an evaluation circuit EC for testing ATM test cells. This evaluation circuit EC includes a circuit ERRC for fault recognition, a circuit HIDC for e.g. cell header recngnition. a circuit TYPD for cell type recognition, a clock LCTI, a circuit SEQE for determining the sequence number. and a circuit DELC for determining a relative or absolut~ transfer time.
The fault recognition circuit ERRC investigates if octets occur in associated pairs which are mutually inverted. To this end a memory. an inverter and a comparison circuit are required for each of the eisht bits.
The errors occurr;ng within an ATM test cell are counted, the counter position of this counter constituting the signal ERR PAT. Further signals are provided: ERR SEQ when an error occurs in the sequence number; ERR TIME when an error occurs in the time indication. and ERR ID when an error occurs in the sequence number. The signals ERR PAT
and ERR ID are also transmitted to thè circuit ~or cell header recognition HIDC.
The so called cell header recognition circuit HIDC
compares the five bytes of the cell header of an incoming cell with the five bytes of a referencP cell. the header bytes each includins a pair of above mentioned bits.
hereafter called PT. which are activated when test or maintenance cells are concerned and which are not activated in the case of data cells. Hereby the output CELL REC is activated when :
- PT i5 activated and when not only the five bytes of the header unit also but also the MCT and MCT bytes are equal; or when - PT i5 not activated and the five bytes of the header are . ~ , ~ .
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equal.
~ hen now CELL REC is activated then the sequence number of the incoming cell i5 compared with that of the reference cell and the output CELL INS i5 thereby activated ~hen :
- these connection numbers are different and there are no errors in the connection number of the incomin~ cell;
- the last mentioned connection number is erroneous and the signal ERR PAT moreover exceeds a predetermined threshold.
The circuit for cell type recognition TYPD
distinsuishes bet~een cells of type TYPE-l and cells of TYPE-û and produces a signal TYPE indicating the cell type.
The circuit SEQE for determining the sequence number e~tracts the sequence number as a 16-bit signal SEQ NR in function of the signal TYPE.
The circuit DELC for determining the relative or absolute transfer time DERLC extracts the time indication TS from the cell in function of the signal TYPE, subtracts it from the local time LTI of the clock LCTI and produces at its output the difference as a 16-bit signal DL. When the clock circuit LT in the test cell generator T6 and the clock LCTI in the evaluation circuit are not runnins in synchronism the absolute transfer time cannot be obtained.
~owever. for a sequence of test calls the relative transfer timP differences may be obtained in this way and these transfer time differences are in general of greater importance than the absolute values of the transfer times.
By the above invention all means are provided for testing the characteristics of an ATM connection.
While the principles of th`e invention have been described abo~e in connection with specific apparatus, it is to be clearly understood that this description is made only by waY of example and not as a limitation on the scope of the invention.
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Claims (20)
1-2 1. Method for testing the characteristics of an ATM
connection between two points of an ATM network.
characterized in that a sequence of test cells is transmitted and tested, the information parts of said cells being built up in an appropriate way with the purpose of recognizing predetermined characteristics of the connection.
connection between two points of an ATM network.
characterized in that a sequence of test cells is transmitted and tested, the information parts of said cells being built up in an appropriate way with the purpose of recognizing predetermined characteristics of the connection.
2. Method according to claim 1, characterized in that the information part of each test cell comprises two parts. the second part being the inverse of the first one.
3. Method according to claim 2. characterized in that both parts are interwoven in such a way that each octet of the first part is immediately followed by the associated inversed octet of the second part.
4. Method according to claim 1, characterized in that each information part includes at least a time indication of the transmission time (TS). a sequence number (SN) in the ATM connection and a connection number (ID), these information being in inverse form or not and that the rest of the information including none of these data contains an indication (FL) that said data are in inverse form or not.
5. Test cell generator with devices for generating the data sequence of an ATM test cell, characterized in that the devices are executed in such a way that the data sequence may selectively, and at least piecewise, be generated in not-inverse form or in inverse form.
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6. Test cell generator according to claim 5, characterized in that the data sequence is realized under the form of octets and is possibly inverted per octet.
7. Test cell generator according to claim 6, characterized in that the devices include : a clock circuit (LT) controlled by the cell clock (CCL), a connection number generator (ID), a write and read memory (MEM), a control circuit (TCGC), a switchable inverter (INV) and an output register (REG).
8. Test cell generator according to claim 7, characterized in that the clock circuit (LT), the connection number generator (ID) and the write and read memory (MEM) are all coupled with the output register (REG) via an inverter (INV) and that all these units are controlled by the control circuit (TCGC).
9. Test cell generator according to claim 8, characterized in that it produces test cells the information part of which at least includes: a time indication (TS) of the sending time, a sequence number (SN) in an ATM connection and a connection number (ID) provided by the clock circuit (LT), the memory (MEM) and the connection number generator (ID) respectively.
10. Test cell generator according to claim 8, characterized in that said memory (MEM) also generates the headers of the test cells.
11. Evaluation circuit for testing ATM test cells.
characterized in that it includes a cell header recognition circuit (HIDC) which by comparing the cell with a test cell is able to find out if an incoming cell is destined to the evaluation circuit (CELC REC) or not.
characterized in that it includes a cell header recognition circuit (HIDC) which by comparing the cell with a test cell is able to find out if an incoming cell is destined to the evaluation circuit (CELC REC) or not.
12. Evaluation circuit according to claim 11, characterized in that the data of the test cell are inverted octet per octet and that there is provided a circuit (TYPD) to find out if the data received are first non inverted and then inverted or vice-versa.
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13. Evaluation circuit according to claim 11, characterized in that the test cells include a time indication (TS) of the sending time and that there is provided a circuit (DELC) to extract said time indication (TS) from a test cell and to calculate the difference thereof with a local time indication (LCTI).
14. Evaluation circuit according to claim 11, characterized in that the cells are provided with a header (H) with a first cell indication (PT) which is activated when a test or maintenance cell and not a data cell is concerned, and that these cells moreover contain an information part including a said cell indication (MCT, ???) which is activated when a test cell is concerned, a time indication (TS) of the sending time of the cell, a sequence number (SN) in an ATM connection and a connection number (ID).
15. Evaluation circuit according to claim 14, characterized in that said cell header recognition circuit (HIDC) compares the header of an incoming cell with that of a reference cell and that when these headers are equal and the first cell indication (PT) is activated it moreover compares the second cell indications (MCT, ???) and in case they are equal provides a first output signal (CELL REC) which indicates that the cell is destined to the evaluation circuit.
16. Evaluation circuit according to claim 15.
characterized in that said first output signal (CELL REC) is also activated when the compared headers are equal, but when the first cell indications (PT) are not activated.
characterized in that said first output signal (CELL REC) is also activated when the compared headers are equal, but when the first cell indications (PT) are not activated.
17. Evaluation circuit according to claim 15 or 16, characterized in that the cell header recognition circuit when the first output signal (CELL REC) is activated also compares the connection number (ID) of the incoming ceIl with that of the reference cell and generates an activated second output signal (CELL INS) when these connection - 11 - J. VAN TETERING - F. DENISSEN
numbers are different and there are no errors in the connection number of the incoming cell, said activated second output signal (CELL INS) indicating an error.
numbers are different and there are no errors in the connection number of the incoming cell, said activated second output signal (CELL INS) indicating an error.
18. Evaluation circuit according to claim 11, characterized in that it includes an error recognition circuit (ERRC) to detect and correct bit errors, the result of this count being indicated by a third output signal (ERR
PAT).
PAT).
19. Evaluation circuit according to claims 14 and 18, characterized in that said error recognition circuit (ERRC) also checks the bit errors in an incoming connection number and upon detection of an error activates a fourth output signal (ERR ID).
20. Evaluation circuit according to claims 17 and 19, characterized in that the second output signal (CELL
INS) is activated when the first output signal (CELL REC) and the fourth output signal (ERR ID) are activated and when the third output signal (ERR PAT) exceeds a predetermined threshold.
INS) is activated when the first output signal (CELL REC) and the fourth output signal (ERR ID) are activated and when the third output signal (ERR PAT) exceeds a predetermined threshold.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| BE9100619 | 1991-06-28 | ||
| BE9100619A BE1004959A3 (en) | 1991-06-28 | 1991-06-28 | Method and device for testing atm connections. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2072516A1 true CA2072516A1 (en) | 1992-12-29 |
Family
ID=3885589
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002072516A Abandoned CA2072516A1 (en) | 1991-06-28 | 1992-06-26 | Method and devices for testing atm connections |
Country Status (11)
| Country | Link |
|---|---|
| US (1) | US5570357A (en) |
| EP (1) | EP0520580B1 (en) |
| JP (1) | JPH05191442A (en) |
| KR (1) | KR0163201B1 (en) |
| AT (1) | ATE168844T1 (en) |
| AU (1) | AU1856292A (en) |
| BE (1) | BE1004959A3 (en) |
| CA (1) | CA2072516A1 (en) |
| DE (1) | DE69226313T2 (en) |
| ES (1) | ES2118785T3 (en) |
| TW (1) | TW211607B (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE470544B (en) * | 1992-11-24 | 1994-07-25 | Ellemtel Utvecklings Ab | For a bit error monitoring in a device intended for selection |
| FR2701618B1 (en) * | 1993-02-16 | 1995-06-23 | Tremel Jean Yves | METHOD FOR MEASURING PERFORMANCE PARAMETERS OF AN ATM NETWORK AND IMPLEMENTATION DEVICE. |
| FR2711466B1 (en) * | 1993-10-20 | 1996-01-26 | Tremel Jean Yves | ATM type telecommunication network test and ATM connection performance measurement. |
| JPH07162435A (en) * | 1993-12-06 | 1995-06-23 | Fujitsu Ltd | Method and device for confirming semi-fixed path |
| US5768300A (en) * | 1996-02-22 | 1998-06-16 | Fujitsu Limited | Interconnect fault detection and localization method and apparatus |
| DE19641398A1 (en) * | 1996-09-27 | 1998-04-02 | Siemens Ag | Method for determining bit errors that have occurred on an ATM transmission path in ATM useful cells with the aid of monitoring OAM cells |
| DE19641399A1 (en) * | 1996-09-27 | 1998-04-02 | Siemens Ag | Method for determining bit errors that have occurred on an ATM transmission path in ATM useful cells with the aid of monitoring OAM cells |
| KR100204061B1 (en) | 1996-12-21 | 1999-06-15 | 이계철 | Subscriber's control module with testing function of atm switching system |
| JP3479248B2 (en) | 1999-12-17 | 2003-12-15 | 日本電気株式会社 | ATM transmission test equipment |
| KR100711658B1 (en) * | 2001-08-28 | 2007-04-27 | 엘지노텔 주식회사 | Test method for e1/t1 link using asynchronous transfer mode network |
| US7355981B2 (en) * | 2001-11-23 | 2008-04-08 | Apparent Networks, Inc. | Signature matching methods and apparatus for performing network diagnostics |
| US8089888B2 (en) * | 2001-12-10 | 2012-01-03 | Qualcomm Incorporated | Method and apparatus for testing traffic and auxiliary channels in a wireless data communication system |
| US7194661B1 (en) * | 2002-12-23 | 2007-03-20 | Intel Corporation | Keep alive buffers (KABs) |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4320881A (en) * | 1980-10-03 | 1982-03-23 | American Standard Inc. | Fail-safe decoder for digital track circuits |
| DE3047239C2 (en) * | 1980-12-16 | 1982-12-30 | Wandel & Goltermann Gmbh & Co, 7412 Eningen | Method and circuit arrangement for measuring the quality of digital transmission links and devices |
| US4551833A (en) * | 1983-08-10 | 1985-11-05 | At&T Bell Laboratories | Distributed monitoring of packet transmission delay |
| JPS61145799A (en) * | 1984-12-20 | 1986-07-03 | Fujitsu Ltd | Semiconductor integrated circuit incorporating memory |
| US4712214A (en) * | 1986-01-10 | 1987-12-08 | International Business Machines Corporation | Protocol for handling transmission errors over asynchronous communication lines |
| US4939746A (en) * | 1987-06-03 | 1990-07-03 | General Electric Company | Trunked radio repeater system |
| DE3786404T2 (en) * | 1987-11-27 | 1994-01-20 | Ibm | Data accuracy control means. |
| DE3912660C1 (en) * | 1989-04-18 | 1990-08-30 | Wandel & Goltermann Gmbh & Co, 7412 Eningen, De | |
| ATE127986T1 (en) * | 1989-06-16 | 1995-09-15 | Siemens Ag | METHOD AND CIRCUIT ARRANGEMENT FOR FORWARDING CELLS TRANSFERRED ACCORDING TO AN ASYNCHRONOUS TRANSFER MODE. |
| DE4014766A1 (en) * | 1990-04-19 | 1992-01-09 | Siemens Ag | Digital transmission path quality parameter evaluation system |
| JPH04127743A (en) * | 1990-09-19 | 1992-04-28 | Fujitsu Ltd | Transmission line testing system for wide band isdn |
| US5422891A (en) * | 1993-07-23 | 1995-06-06 | Rutgers University | Robust delay fault built-in self-testing method and apparatus |
-
1991
- 1991-06-28 BE BE9100619A patent/BE1004959A3/en not_active IP Right Cessation
-
1992
- 1992-06-22 AU AU18562/92A patent/AU1856292A/en not_active Abandoned
- 1992-06-24 US US07/903,364 patent/US5570357A/en not_active Expired - Fee Related
- 1992-06-25 DE DE69226313T patent/DE69226313T2/en not_active Expired - Fee Related
- 1992-06-25 AT AT92201878T patent/ATE168844T1/en not_active IP Right Cessation
- 1992-06-25 EP EP92201878A patent/EP0520580B1/en not_active Expired - Lifetime
- 1992-06-25 ES ES92201878T patent/ES2118785T3/en not_active Expired - Lifetime
- 1992-06-26 CA CA002072516A patent/CA2072516A1/en not_active Abandoned
- 1992-06-27 KR KR1019920011442A patent/KR0163201B1/en not_active IP Right Cessation
- 1992-06-29 JP JP4171314A patent/JPH05191442A/en active Pending
- 1992-06-30 TW TW081105171A patent/TW211607B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| ATE168844T1 (en) | 1998-08-15 |
| US5570357A (en) | 1996-10-29 |
| EP0520580A1 (en) | 1992-12-30 |
| ES2118785T3 (en) | 1998-10-01 |
| BE1004959A3 (en) | 1993-03-02 |
| EP0520580B1 (en) | 1998-07-22 |
| DE69226313T2 (en) | 1998-12-03 |
| KR930001627A (en) | 1993-01-16 |
| TW211607B (en) | 1993-08-21 |
| JPH05191442A (en) | 1993-07-30 |
| KR0163201B1 (en) | 1998-12-01 |
| AU1856292A (en) | 1993-01-07 |
| DE69226313D1 (en) | 1998-08-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Discontinued |