CA2039715A1 - Data processing system and process for controlling it and cpu boards - Google Patents

Data processing system and process for controlling it and cpu boards

Info

Publication number
CA2039715A1
CA2039715A1 CA 2039715 CA2039715A CA2039715A1 CA 2039715 A1 CA2039715 A1 CA 2039715A1 CA 2039715 CA2039715 CA 2039715 CA 2039715 A CA2039715 A CA 2039715A CA 2039715 A1 CA2039715 A1 CA 2039715A1
Authority
CA
Canada
Prior art keywords
cpu
main memory
bus
connection
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA 2039715
Other languages
English (en)
French (fr)
Inventor
Thomas Schlage
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2039715A1 publication Critical patent/CA2039715A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Image Processing (AREA)
  • Multi Processors (AREA)
CA 2039715 1989-08-23 1990-08-23 Data processing system and process for controlling it and cpu boards Abandoned CA2039715A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEG8910102.2 1989-08-23
DE8910102 1989-08-23

Publications (1)

Publication Number Publication Date
CA2039715A1 true CA2039715A1 (en) 1991-02-24

Family

ID=6842240

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2039715 Abandoned CA2039715A1 (en) 1989-08-23 1990-08-23 Data processing system and process for controlling it and cpu boards

Country Status (5)

Country Link
EP (1) EP0439591A1 (ja)
JP (1) JPH06105447B2 (ja)
AU (1) AU6164090A (ja)
CA (1) CA2039715A1 (ja)
WO (1) WO1991003020A1 (ja)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1485758A (en) * 1973-09-16 1977-09-14 Hawker Siddeley Dynamics Ltd Computer systems
JPS5533268A (en) * 1978-08-31 1980-03-08 Toshiba Corp Dma system for electronic computer
JPS564854A (en) * 1979-06-22 1981-01-19 Fanuc Ltd Control system for plural microprocessors
JPS58140862A (ja) * 1982-02-16 1983-08-20 Toshiba Corp 相互排他方式
JPS62231367A (ja) * 1986-04-01 1987-10-09 Meidensha Electric Mfg Co Ltd Ｄｍａデ−タ転送方式
US4771286A (en) * 1986-07-28 1988-09-13 Honeywell Bull Inc. Lan controller having split bus design

Also Published As

Publication number Publication date
JPH06105447B2 (ja) 1994-12-21
AU6164090A (en) 1991-04-03
WO1991003020A1 (de) 1991-03-07
JPH04502975A (ja) 1992-05-28
EP0439591A1 (de) 1991-08-07

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Legal Events

Date Code Title Description
FZDE Dead