CA2000376A1 - Processeur vectoriel utilisant un tampon pour preparer les doennees vectorielles - Google Patents

Processeur vectoriel utilisant un tampon pour preparer les doennees vectorielles

Info

Publication number
CA2000376A1
CA2000376A1 CA2000376A CA2000376A CA2000376A1 CA 2000376 A1 CA2000376 A1 CA 2000376A1 CA 2000376 A CA2000376 A CA 2000376A CA 2000376 A CA2000376 A CA 2000376A CA 2000376 A1 CA2000376 A1 CA 2000376A1
Authority
CA
Canada
Prior art keywords
vector
instruction
buffer
contention
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2000376A
Other languages
English (en)
Other versions
CA2000376C (fr
Inventor
Hideo Hayashi
Atsuo Mochizuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CA2000376A1 publication Critical patent/CA2000376A1/fr
Application granted granted Critical
Publication of CA2000376C publication Critical patent/CA2000376C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8061—Details on data memory access
    • G06F15/8069—Details on data memory access using a cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
CA002000376A 1988-10-11 1989-10-10 Processeur vectoriel utilisant un tampon pour preparer les doennees vectorielles Expired - Fee Related CA2000376C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63255600A JP2531760B2 (ja) 1988-10-11 1988-10-11 ベクトル処理装置
JP63-255600 1988-10-11

Publications (2)

Publication Number Publication Date
CA2000376A1 true CA2000376A1 (fr) 1990-04-11
CA2000376C CA2000376C (fr) 1994-05-31

Family

ID=17280979

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002000376A Expired - Fee Related CA2000376C (fr) 1988-10-11 1989-10-10 Processeur vectoriel utilisant un tampon pour preparer les doennees vectorielles

Country Status (5)

Country Link
US (1) US5237702A (fr)
EP (1) EP0363889B1 (fr)
JP (1) JP2531760B2 (fr)
CA (1) CA2000376C (fr)
DE (1) DE68927659T2 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU1804645C (ru) * 1991-03-27 1993-03-23 Институт Точной Механики И Вычислительной Техники Им.С.А.Лебедева Центральный процессор
FR2676845B1 (fr) * 1991-05-23 1993-09-24 Sextant Avionique Dispositif pour la gestion de plusieurs files d'attente independantes dans un espace memoire commun et banalise.
US5809552A (en) * 1992-01-29 1998-09-15 Fujitsu Limited Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions
JPH06203057A (ja) * 1992-09-28 1994-07-22 Nec Corp ベクトル演算処理装置とその並列制御方式と並列制御回路
US5881302A (en) * 1994-05-31 1999-03-09 Nec Corporation Vector processing unit with reconfigurable data buffer
US5689653A (en) * 1995-02-06 1997-11-18 Hewlett-Packard Company Vector memory operations
CN1160622C (zh) * 1996-03-28 2004-08-04 皇家菲利浦电子有限公司 在顺序处理器上处理数据元素集合的方法和计算机系统
US7272703B2 (en) * 1997-08-01 2007-09-18 Micron Technology, Inc. Program controlled embedded-DRAM-DSP architecture and methods
US6813701B1 (en) * 1999-08-17 2004-11-02 Nec Electronics America, Inc. Method and apparatus for transferring vector data between memory and a register file
TWI250632B (en) * 2003-05-28 2006-03-01 Siliconware Precision Industries Co Ltd Ground-enhancing semiconductor package and lead frame
US7447873B1 (en) * 2005-11-29 2008-11-04 Nvidia Corporation Multithreaded SIMD parallel processor with loading of groups of threads
US7594095B1 (en) * 2005-11-29 2009-09-22 Nvidia Corporation Multithreaded SIMD parallel processor with launching of groups of threads
JP4687729B2 (ja) * 2008-03-04 2011-05-25 日本電気株式会社 キャッシュメモリ及びベクトル処理装置並びにベクトルデータ整列方法
WO2014107148A1 (fr) 2013-01-03 2014-07-10 Intel Corporation Pré-extraction adaptative de données
CN111651201B (zh) * 2016-04-26 2023-06-13 中科寒武纪科技股份有限公司 一种用于执行向量合并运算的装置和方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5975365A (ja) * 1982-10-22 1984-04-28 Hitachi Ltd ベクトル処理装置
JPS62180470A (ja) * 1986-02-04 1987-08-07 Hitachi Ltd ベクトル処理装置
JPS62288974A (ja) * 1986-06-09 1987-12-15 Hitachi Ltd ベクトル処理装置
US5010477A (en) * 1986-10-17 1991-04-23 Hitachi, Ltd. Method and apparatus for transferring vector data between parallel processing system with registers & logic for inter-processor data communication independents of processing operations
US4772049A (en) * 1987-06-01 1988-09-20 Ncr Corporation Multiple ply document
US4949250A (en) * 1988-03-18 1990-08-14 Digital Equipment Corporation Method and apparatus for executing instructions for a vector processing system

Also Published As

Publication number Publication date
EP0363889B1 (fr) 1997-01-15
EP0363889A1 (fr) 1990-04-18
DE68927659D1 (de) 1997-02-27
JPH02101576A (ja) 1990-04-13
CA2000376C (fr) 1994-05-31
DE68927659T2 (de) 1997-05-07
US5237702A (en) 1993-08-17
JP2531760B2 (ja) 1996-09-04

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Legal Events

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MKLA Lapsed