CA1291266C - Bcd adder circuit - Google Patents

Bcd adder circuit

Info

Publication number
CA1291266C
CA1291266C CA000571531A CA571531A CA1291266C CA 1291266 C CA1291266 C CA 1291266C CA 000571531 A CA000571531 A CA 000571531A CA 571531 A CA571531 A CA 571531A CA 1291266 C CA1291266 C CA 1291266C
Authority
CA
Canada
Prior art keywords
vector
bcd
carry
sum
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000571531A
Other languages
English (en)
French (fr)
Inventor
Virginia C. Lamere
Matthew J. Adiletta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of CA1291266C publication Critical patent/CA1291266C/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4921—Single digit adding or subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
CA000571531A 1987-07-09 1988-07-08 Bcd adder circuit Expired CA1291266C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US072,161 1987-07-09
US07/072,161 US4805131A (en) 1987-07-09 1987-07-09 BCD adder circuit

Publications (1)

Publication Number Publication Date
CA1291266C true CA1291266C (en) 1991-10-22

Family

ID=22105974

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000571531A Expired CA1291266C (en) 1987-07-09 1988-07-08 Bcd adder circuit

Country Status (6)

Country Link
US (1) US4805131A (OSRAM)
EP (1) EP0298717A3 (OSRAM)
JP (1) JPS6488737A (OSRAM)
CN (1) CN1014188B (OSRAM)
BR (1) BR8803463A (OSRAM)
CA (1) CA1291266C (OSRAM)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5699287A (en) * 1992-09-30 1997-12-16 Texas Instruments Incorporated Method and device for adding and subtracting thermometer coded data
GB9510834D0 (en) * 1995-05-27 1995-07-19 Int Computers Ltd Decimal arithmetic apparatus and method
US6055557A (en) * 1997-01-08 2000-04-25 International Business Machines Corp. Adder circuit and method therefor
US7299254B2 (en) 2003-11-24 2007-11-20 International Business Machines Corporation Binary coded decimal addition
US7546328B2 (en) * 2004-08-31 2009-06-09 Wisconsin Alumni Research Foundation Decimal floating-point adder
US7743084B2 (en) * 2004-09-23 2010-06-22 Wisconsin Alumni Research Foundation Processing unit having multioperand decimal addition
US7519645B2 (en) * 2005-02-10 2009-04-14 International Business Machines Corporation System and method for performing decimal floating point addition
US7477171B2 (en) * 2007-03-27 2009-01-13 Intel Corporation Binary-to-BCD conversion
RU2402803C2 (ru) * 2007-12-14 2010-10-27 Борис Михайлович Власов Способ и устройство суммирования двоично-десятичных чисел
CN102591614B (zh) * 2011-01-14 2015-09-09 上海丽恒光微电子科技有限公司 加法器以及集成电路
US9143159B2 (en) * 2012-10-04 2015-09-22 Silminds, Inc. DPD/BCD to BID converters
US9134958B2 (en) * 2012-10-22 2015-09-15 Silminds, Inc. Bid to BCD/DPD converters
US9400635B1 (en) 2013-01-14 2016-07-26 Altera Corporation Methods and apparatus for performing dynamic data alignment for floating-point operations
US10671345B2 (en) 2017-02-02 2020-06-02 Intel Corporation Methods and apparatus for performing fixed-point normalization using floating-point functional blocks
CN108268242B (zh) * 2018-02-11 2021-09-28 山东理工大学 一种10:4进位存储加法器和10:2进位存储加法器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629565A (en) * 1970-02-13 1971-12-21 Ibm Improved decimal adder for directly implementing bcd addition utilizing logic circuitry
US3711693A (en) * 1971-06-30 1973-01-16 Honeywell Inf Systems Modular bcd and binary arithmetic and logical system
DE2352686B2 (de) * 1973-10-20 1978-05-11 Vereinigte Flugtechnische Werke- Fokker Gmbh, 2800 Bremen Dezimaler Parallel-Addierer/Substrahierer
US4001570A (en) * 1975-06-17 1977-01-04 International Business Machines Corporation Arithmetic unit for a digital data processor
US4172288A (en) * 1976-03-08 1979-10-23 Motorola, Inc. Binary or BCD adder with precorrected result
US4638300A (en) * 1982-05-10 1987-01-20 Advanced Micro Devices, Inc. Central processing unit having built-in BCD operation
US4707799A (en) * 1984-01-30 1987-11-17 Kabushiki Kaisha Toshiba Bit sliced decimal adding/subtracting unit for multi-digit decimal addition and subtraction
JPS61166627A (ja) * 1985-01-18 1986-07-28 Toshiba Corp １０進桁加減算回路
WO1986004699A1 (en) * 1985-01-31 1986-08-14 Burroughs Corporation Fast bcd/binary adder
US4718033A (en) * 1985-06-28 1988-01-05 Hewlett-Packard Company Intermediate decimal correction for sequential addition

Also Published As

Publication number Publication date
JPH0545982B2 (OSRAM) 1993-07-12
EP0298717A3 (en) 1991-01-16
JPS6488737A (en) 1989-04-03
CN1031613A (zh) 1989-03-08
US4805131A (en) 1989-02-14
EP0298717A2 (en) 1989-01-11
CN1014188B (zh) 1991-10-02
BR8803463A (pt) 1989-01-31

Similar Documents

Publication Publication Date Title
CA1291266C (en) Bcd adder circuit
US4785393A (en) 32-Bit extended function arithmetic-logic unit on a single chip
US5497340A (en) Apparatus and method for detecting an overflow when shifting N bits of data
US4623982A (en) Conditional carry techniques for digital processors
US4866656A (en) High-speed binary and decimal arithmetic logic unit
US6820107B1 (en) Square root extraction circuit and floating-point square root extraction device
US4761760A (en) Digital adder-subtracter with tentative result correction circuit
WO1993022721A1 (en) Compact multiplier
US5943251A (en) Adder which handles multiple data with different data types
US4138731A (en) High speed binary and binary coded decimal adder
US4172288A (en) Binary or BCD adder with precorrected result
JPS6143341A (ja) 加算回路
JPH0391832A (ja) 加算回路
US5745399A (en) Decimal arithmetic apparatus and method
US4644491A (en) Sign generation system for a carry save adder
US5007010A (en) Fast BCD/binary adder
US4700325A (en) Binary tree calculations on monolithic integrated circuits
US4545028A (en) Partial product accumulation in high performance multipliers
US6546411B1 (en) High-speed radix 100 parallel adder
EP0361886B1 (en) Improved floating point computation unit
EP0044450B1 (en) Digital adder circuit
US5307302A (en) Square root operation device
JP2554452B2 (ja) 自己検査型補数加算器ユニット
JPS61166628A (ja) 除算装置
US5142490A (en) Multiplication circuit with storing means

Legal Events

Date Code Title Description
MKLA Lapsed