CA1275309C - Low jitter digital delay generator - Google Patents

Low jitter digital delay generator

Info

Publication number
CA1275309C
CA1275309C CA000521923A CA521923A CA1275309C CA 1275309 C CA1275309 C CA 1275309C CA 000521923 A CA000521923 A CA 000521923A CA 521923 A CA521923 A CA 521923A CA 1275309 C CA1275309 C CA 1275309C
Authority
CA
Canada
Prior art keywords
stage
output
stages
input
decoded indication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA000521923A
Other languages
English (en)
French (fr)
Inventor
Agoston Agoston
George J. Caspell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Application granted granted Critical
Publication of CA1275309C publication Critical patent/CA1275309C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/665—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Details Of Television Scanning (AREA)
  • Gasification And Melting Of Waste (AREA)
  • Saccharide Compounds (AREA)
  • Manipulation Of Pulses (AREA)
CA000521923A 1986-03-28 1986-10-31 Low jitter digital delay generator Expired - Fee Related CA1275309C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US845,282 1986-03-28
US06/845,282 US4726045A (en) 1986-03-28 1986-03-28 Low jitter digital delay generator

Publications (1)

Publication Number Publication Date
CA1275309C true CA1275309C (en) 1990-10-16

Family

ID=25294854

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000521923A Expired - Fee Related CA1275309C (en) 1986-03-28 1986-10-31 Low jitter digital delay generator

Country Status (5)

Country Link
US (1) US4726045A (enrdf_load_stackoverflow)
EP (1) EP0238747B1 (enrdf_load_stackoverflow)
JP (1) JPS631115A (enrdf_load_stackoverflow)
CA (1) CA1275309C (enrdf_load_stackoverflow)
DE (1) DE3682766D1 (enrdf_load_stackoverflow)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4891825A (en) * 1988-02-09 1990-01-02 Motorola, Inc. Fully synchronized programmable counter with a near 50% duty cycle output signal
US4879730A (en) * 1988-05-31 1989-11-07 Siemens Transmission Systems, Inc. Jitter tolerant circuit for dual rail data
US5048064A (en) * 1988-11-04 1991-09-10 General Signal Corporation Vital rate decoder
US5060243A (en) * 1990-05-29 1991-10-22 Motorola, Inc. Ripple counter with reverse-propagated zero detection
JPH04117727A (ja) * 1990-09-06 1992-04-17 Mitsubishi Electric Corp カウンター回路
DE4037062C2 (de) * 1990-11-22 1996-05-23 Broadcast Television Syst Schaltungsanordnung zur Synchronisierung eines asynchronen Datensignals
US5093581A (en) * 1990-12-03 1992-03-03 Thomson, S.A. Circuitry for generating pulses of variable widths from binary input data
US5124573A (en) * 1990-12-20 1992-06-23 International Business Machines Adjustable clock chopper/expander circuit
US5278456A (en) * 1991-06-24 1994-01-11 International Business Machines Corporation Process independent digital clock signal shaping network
US5179294A (en) * 1991-06-24 1993-01-12 International Business Machines Corporation Process independent digital clock signal shaping network
US5357153A (en) * 1993-01-28 1994-10-18 Xilinx, Inc. Macrocell with product-term cascade and improved flip flop utilization
JP2998889B2 (ja) * 1994-04-28 2000-01-17 キヤノン株式会社 無線通信システム
JP3505011B2 (ja) * 1995-06-22 2004-03-08 株式会社アドバンテスト 高精度信号発生回路
US6380785B2 (en) * 1999-02-01 2002-04-30 Agilent Technologies, Inc. Method and apparatus for eliminating shoot-through events during master-slave flip-flop scan operations
JP4965203B2 (ja) * 2006-09-11 2012-07-04 株式会社リコー 遅延時間生成回路、それを用いた二次電池保護用半導体装置、バッテリパックおよび電子機器
CN101652926B (zh) 2007-04-10 2012-05-23 Nxp股份有限公司 高频计数器及其计数方法
US8644447B2 (en) * 2008-11-26 2014-02-04 Stmicroelectronics International N.V. System and a method for generating time bases in low power domain
TWI399925B (zh) * 2010-01-20 2013-06-21 Socle Technology Corp 濾波電路及具有濾波電路之系統晶片
TWI538402B (zh) * 2014-06-04 2016-06-11 新唐科技股份有限公司 計數器
US10742220B1 (en) * 2019-04-30 2020-08-11 Synopsys, Inc. Method and apparatus for operating programmable clock divider using reset paths

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3391305A (en) * 1965-04-28 1968-07-02 New York Air Brake Co Timer unit having selectable rest position
FR2109515A5 (enrdf_load_stackoverflow) * 1970-10-30 1972-05-26 Comp Generale Electricite
US3774056A (en) * 1971-04-29 1973-11-20 Design And Manuf Corp Digital electronic control circuit for cyclically operable appliances and the like
US3833854A (en) * 1972-12-14 1974-09-03 Singer Co Digital phase shifter
US3942124A (en) * 1973-12-26 1976-03-02 Tarczy Hornoch Zoltan Pulse synchronizing apparatus and method
SU657618A1 (ru) * 1976-09-23 1979-04-15 Таганрогский радиотехнический институт им. В.Д.Калмыкова Делитель частоты импульсов
JPS5698940A (en) * 1980-01-11 1981-08-08 Toshiba Corp Frequency division circuit
JPS56158534A (en) * 1980-05-10 1981-12-07 Nippon Gakki Seizo Kk Programmable counter
JPS57157630A (en) * 1981-03-25 1982-09-29 Nakamichi Corp Signal converting circuit
JPS5923983A (ja) * 1982-07-30 1984-02-07 Toshiba Corp サンプリングパルス発生回路
US4622481A (en) * 1985-08-21 1986-11-11 Rca Corporation Digital envelope detection circuit

Also Published As

Publication number Publication date
EP0238747A2 (en) 1987-09-30
DE3682766D1 (de) 1992-01-16
EP0238747A3 (en) 1989-02-08
EP0238747B1 (en) 1991-12-04
JPH0467811B2 (enrdf_load_stackoverflow) 1992-10-29
JPS631115A (ja) 1988-01-06
US4726045A (en) 1988-02-16

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