US3659091A

US3659091A - Method and circuit for continuously evaluating deviations by counting

Info

Publication number: US3659091A
Application number: US792256*A
Authority: US
Inventors: Heinz Holzem; Hans-Joachim Henning
Original assignee: A Pierburg KG
Current assignee: Pierburg Luftfahrtgerate Union GmbH; A Pierburg KG
Priority date: 1968-01-20
Filing date: 1969-01-21
Publication date: 1972-04-25
Anticipated expiration: 1989-04-25
Also published as: GB1227722A; FR2000483A1; FR2000483B1

Abstract

The invention relates to a method and circuitry for continuously evaluating deviations between the measured value and the desired value of a quantity occurring in the form of a sequence of pulses. A counter which functions according to the Aiken code is preset to the complement of a particular desired value, the measured value is fed in the form of a sequence of pulses into the preset counter during a definite interval of time and the difference between the measured value and the desired value is transferred in the form of an Aiken coded number during a second time interval to a memory unit. The Aiken coded number in the memory is then inverted if there has been non-transition through the zero by the counter, the number which is then delivered by the memory being given a polarity opposite to that which would result from a zero transition.

Description

United States Patent Holzem et al.

[54] METHOD AND CIRCUIT FOR 3,161,765 12/1964 Hoberg et al. ..235/l76 CONTINUOUSLY EVALUATING 3,312,612 5/1967 Diller... ..235/ 176 DEVIATIONS BY COUNTING Primary Examiner-Malcolm A. Morrison [72] Inventors: Heinz Holzem, Monchengladbach; Hans- AMI-mm Examiner' .1)avid Malzahn Joachim Hennlns, Neuss. t of Attorney-Curt M. Avery, Arthur E. Wilfond, Herbert 1.. y Lerner and Daniel J. Tick [73] Assignee: Pierburg Luftfahrtgerate Union GmbH, I

' Neuss am Rhein, Germany [57] ABSTRACT [22] Filed; Jam 21, 1969 The invention relates to a method and circuitry for continuously evaluating deviations between the measured value and [21] PP 792356 the desired value of a quantity occurring in the form of a sequence of pulses. A counter which functions according to (30] Foreign A fi afi p i i Dan the Aiken code is preset to the complement of a particular I desired value, the measured value is fed in the form of a Jan 1968 Germany 16 38 1003 sequence ofpulses into the preset counter during a definite interval of time and the difference between the measured value 521 u.s.c1 ..235/177, 235/176 and the desired value is transferred in the form of an Aiken [51 1 Cl. t I ..G06f c ed numbe du ng a e n time interval to a memory unit- [58] Field of Search ..236/l77, 176, 168,92 CA The Aiken coded number in the memory is the inverted if 6 R f d there has been non-transition through the zero by the counter, [5 1 e erences Ie the number'which is then delivered by the memory being UNITED STATES PATENTS given a polarity opposite to that which would result from a zero transmon.

2,917,236 l2/1959 Reisch ..235/l76 2,956,748 10/1960 Weissman ..235/I 76 9 Claims, 9 Drawing Figures 0-1 CONVERTER L 22b 2 J 220 MEMORY 5

21b

11, 100 blc d e b c DISCRIMINATOR smmc SW'ICH INVERTOR PATENTEDAFR 25 1912 3, 659 O91 SHEET 2B? 5 [I000 ISIS 9999 C(IMPLE4 DESIRED m1 MENTI MEASURED 1.106

COMPLEMENLOF DEVIATION DEVIATION 1.195

FIG. 3a

COMPLEMENT mssmw: 1.186

GOUNTING couurmc MEASURED: 8381 DEVIATION/ FlG 3b LOGIC TABLE FOR BISTABLE FLIP-FLOP SIGNAL STATE DURING SIGNAL STATE AT UUTPUTQ UPON RELEASING PULSE AN ARRIVAL 0F RELEASING PULSE UNCHANGED 0 ANDU INVERT THEIR SIGNAL arms SIGNAL L AT RESET INPUT SETS 0 T0 L ARROWS AT TRIGGER INPUT:

FULL HEAD: FLIP-FLOP TRIGGERED WITH DECENDING PULSE ELANK.

EMPTYHEAD: FLIP-FLOP TRIGGERED WITH ASGENDING PULSE TLANII.

FIG. 7

PATENTEB APR 2 5 1972 SHEET 3 GF 5 =NF 2 cmmnmmqnmw ammmmmqn- :i a q :2 i 21.2 i 5 g PATENTEDAPRZSWZ 3,659,081

SHEET u 0F 5 IIIES 53 lllllll 1L3 METHOD AND CIRCUIT FOR CONTINUOUSLY EVALUATING DEVIATIONS BY COUNTING The present invention relates to a method of continuously evaluating the deviation between the measured value and the desired value of a quantity in the form of a sequence of pulses, the method enabling the evaluated deviation to be used for continuously monitoring and controlling the measured value. The invention also relates to an electric circuit for putting this method into effect.

In known methods of this kind there is used for example a forwards-backwards counter, one input of which is fed with a sequence of pulses corresponding to the desired value, and the other input of which is fed with a sequence of pulses corresponding to the measured value. The counter determines the difference between the two values. However in a method of this kind there can occur coincidence between the two sequences of pulses, and this impairs the accuracy of measurement. Furthermore difficulties are encountered in allowing for the polarity of the deviation.

In other known methods the desired value is fed to a digital computer, either in the form of a sequence of pulses, or simply as a pre-set number. The measured quantity is fed into the input of the computer. This method has the advantage compared to the previously mentioned method that the desired value is pre-set in the form of a static number, and consequently coincidence cannot occur. On the other hand it is a costly method because it involves the use of a digital computer. This method is therefore often inapplicable for economic reasons.

The object of the present invention is to provide a method which allows continuous monitoring of the deviation of a quantity which occurs in the form of pulses, the deviation being evaluated with great precision and reliability and very rapidly, but at little cost. The method should allow the deviation to be detected, and should allow a signal to be derived which expresses the value and polarity of the deviation in such a way that the signal can be used for continuously controlling the measured value to make it agree with the desired value.

In accordance with the invention, in a method of continuously evaluating deviations between the measured value and the desired value of a quantity occurring in the form of a sequence of pulses, a counter which functions according to the Aiken Code is pre-set to the complement of the particular desired value, the measured value is fed in the form of a sequence of pulses into the pre-set counter during a definite interval of time the difference between the measured value and the desired value, as determined by the counter, is transferred in the form of an Aiken Coded number during a second definite interval of time of a memory unit, which also functions according to the Aiken Code, the Aiken Coded number in the memory being then inverted if there has been nontransition through zero by the counter, the number which is then delivered by the memory being given a polarity opposite to that which would result from a zero transition.

The invention also includes a circuit for carrying out this method the circuit comprising a counter constructed of bistable flip-flops, the counter being connected to a number setting switch for pre-setting the counter to the complement of the Aiken Coded desired value, the counter having an input terminal which can be connected, over a first AND gate which can be blocked during the second time interval, to a lead for conveying the sequence of measured value pulses, the counter also having output terminals connected to the B input terminals of a NAND gate, the output terminals of which are connected to the signal input terminals of a memory consisting of further bistable flip-flops, the A input terminals of the NAND gate being connected to a pulse lead which is arranged to carry a potential, during a part of the second time interval, suitable for opening the NAND gates so that the number stored in the counter reaches the input terminals of the flipflops of the memory, which also have triggering input terminals connected to a lead which conveys triggering pulses.

The invention will now be described by way of example with reference to the drawing, in which:

FIG. 1 is a block diagram showing a combination of functional units;

FIG. 2 is a table showing the Aiken Code;

FIG. 30 represents the action of the counter, when it is set to the complement of a particular desired value and then adds the measured value, without passing through its zero value;

FIG. 3b represents the same process as shown in FIG. 3a, but in this case the adding of the measured value causes the counter to pass through its zero position; 1

FIG. 4 is a block diagram corresponding essentially to FIG. I, but showing the construction of the circuit;

FIG. 5 is a block diagram showing an arrangement for timecontrolling the circuit shown in FIG. 4, the arrangement consisting of a rhythmic pulser which feeds a logical circuit;

FIG. 6a represents the sequence of pulses delivered by the circuit for the case represented in FIG. 3a, where the counter undergoes no zero transition;

FIG. 612 represents the sequence of pulses for the case shown in FIG. 3b, in which the counter undergoes a zero transition;

FIG. 7 is a table which describes the switching behavior of a bistable flip-flop (master-slave flip-flop) in the operation of the method.

The principle of the construction of the circuit according to the invention will first be described with reference to FIG. I.

A counter 10 is connected by leads 12a, 12b and 12c, and

others if necessary, to a number-setting switch 12, which sets the counter 10 to the complement of a number which corresponds to the desired value. Over a measured value input lead 14 there is fed to the counter 10 a sequence of pulses which represent the measured value. This sequence of pulses is fed to the counter intermittently, that is to say the input lead 14 is opened intermittently for equal open periods, being closed briefly between the open periods, so that during each open period a number of pulses reach the counter, the number depending on the measured value. When the input lead 14 is blocked, there prevails on the output terminals of the counter a numerical value which is the difierence between the measured value and the pre-set desired value. This numerical value is delivered over the leads 10a, 10b, 10c etc. to a memory unit 16, the output of which feeds, through a connection 28, a digital-to-analog converter 18 of known kind, which delivers at its output an analog signal representing the deviation of the measured value from the desired value.

The zero output terminal of the counter 10 is connected to a zero discriminator 22, which detects whether the counter 10 has run through its zero position or not. If the zero position has been run through, an AND-gate 21b is blocked, and consequently no signal passes over output leads 22a and 22b of the AND-gate 21b, from an invertor 21a, which produces rhythmic inversion signals. In the other case, that is to say if the counter 10 has not passed through its zero position, the zero discriminator 22 opens the AND-gate 21b, allowing the inversion signals produced by the invertor 21 to pass over the leads 22a, 22b. The signal passing over the lead 22a inverts the value in the memory 16, as will be described in greater detail below. The signal passing over the lead 22b activates a pole reverser 20, with the result that the output leads of the digitalto-analog converter 18 are connected pole reversed to the output terminals 32a, 32b of the circuit, that is to say the connections are pole reversed with respect to their positions after a zero transition has occurred, in the counter 10.

The counter 10 the number setting switch 12 and the memory 16 all function on the basis of the Aiken Code. Although the Aiken Code is in itself known, for the sake of completeness FIG. 2 shows the relationship between the decimal system and the Aiken Code.

The behavior of the counter 10, when the Aiken Code is used, is illustrated diagramatically in FIGS. 30 and 3b, assuming that numbers containing four decades are used, the counter being therefore capable of counting from 0000 up to 9999.

Case I. No zero transition. FIG. 3a

The desired value in 8381, and the number setting switch sets the counter to the complementary value 1618. The detected measured value is 4186. The counter counts forwards from 1618 up to the value 5804. The difference between the measured value and the desired value is 8381 less 4186, that is to say 4195. The counter delivers the complement of this deviation, that is to say the number 5804. This value is delivered to the memory unit 16.

In this case the counter has not passed through its zero position, and consequently the AND-gate 21b is open. An inversion pulse from the inverter 21a reaches the memory 16 and inverts the value. memorize, so that on the output terminal of the memory there now appears the numerical value which correctly represents the deviation between the measured value and the desired value. Simultaneously, a signal passing over the line 22b changes the pole reversing switch 20 to its other position.

Case 2. Zero transition. FIG. 3b

In this case the desired value is 4186, and the number setting switch 12 sets the complementary value 5813 on the counter 10. The measured value is 8381. The counter, counting forwards, passes through its zero position and then counts up to 4195. The difference between the measured value and the desired value is time 4186 less 8381, that is to say 4195, but in this case it has a negative sign.

In this case the value delivered by the counter is the true deviation, not the complement of the deviation. This true deviation value is delivered by the counter 10 to the memory 16, and it must not be inverted. When the counter was passing through its zero position it triggered the zero discriminator 22, to the effect that the AND-gate 21b remains blocked, and consequently the invertor 21a cannot deliver an invertion pulse. No signal passes over the lead 22b to the pole reverser, which consequently retains its first position, that is to say the output terminals 32a, 32b of the circuit remain connected in the first position, corresponding to the fact that the deviation value is delivered with a negative sign.

The block diagram shown in FIG. 4 illustrates in greater detail a circuit according to the invention, based on the principles represented in FIG. 1.

In FIG. 4, the counter 10 consists of individual decade counters 10, 10" etc., each of which consists of bistable flipflops (master-slave flip-flops) arranged in the known way. The flip-flops function according to the Aiken Code. Number setting switches 12, 12'. etc. are connected over leads 12a, l2'b, l2'cetc. and 12 '5, 12 'b, 12 '6 etc. to the individual flip-flops of the decade counters 10', 10" etc. The number setting switches set the counters to the complement of the desired value. An input terminal 13 of the decade counter 10' is connected to the measured value input lead 14 over an AND-gate 24. This AND-gate 24 is opened intermittently, each time for a definite period of time t,, and then closed briefly during a second definite period of time 1 The output terminals of the decade counters L, 10 etc., and also their complementary output terminals Q, are connected to the 13 input terminals of NAND-gates 26, whose output terminals are connected to the signal input terminals .1, K of bistable flip-flops (master-slave flip-flops) 16'a, l6b, l6c,etc. and 16 'b 16"b, 16"oetc. which also function on the basis of the Aiken Code. The input terminals A of the gates 26 are all connected together to a pulse conductor 76, over which the gates 26 can be opened and closed.

In addition to the signal input terminals J, K, the flip-flops 16', 16" etc. also have triggering input terminals 17 connected to a triggering pulse lead 36. The Q outputs of the flipflops 16 are connected over leads 28 to a suitably weighted digital-to-analog converter 18, which delivers, over the

output terminals

30a, 30b, an analog signal which represents the deviation between the measured value and the desired value, as determined by the circuit. Signal leads 32a, 32b, which are connected to the subsequent process controlling device, are connected with alternative polarity to the

terminals

30a, 30b, by the pole reversing action of the pole reversing assembly 20.

The reversing of the poles can be effected by means of a relay 34 connected to a control lead 80, which corresponds to the lead 22b in FIG. 1 and whose method of functioning will be described further below.

Before describing the method of functioning of the circuit shown in FIG. 4, there will first be described the construction of the rhythmic pulser shown in FIG. 5. This circuit is used for controlling the individual functional stages of the complex represented in FIG. 4. The principal sequences of pulses delivered, directly or indirectly, by the circuit of FIG. 4 are represented in FIGS. 6a and 6b.

The rhythmic pulser consists essentially of a pulse generator 40 and a logic circuit 42, which is controlled by the pulse generator 40. The pulse generator 40 contains a frequency stable, preferably quartz-controlled oscillator 44, which produces rhythmic pulses. The trailing flanks control, over an output terminal 45, a counter which functions as a frequency divider 46, which has decadic stages 46', 46 etc. In the present example the frequency divider 6 comprises three full decades and a half a decade, this division giving a better measurement cycle, corresponding to each passage through the frequency divider 46. In principle this frequency divider can if desired be constructed in the form of a dual divider. The first digits 1 to 6 of the ones-decade 46 deliver, over the leads 46, to 46 to the

leads

51, 52, 53, 54, 55, 56 a first, second, up to sixth rhythmic pulse. In FIGS. 6a and 6b the pulses delivered by the oscillator 44 are shown in line 45, at the top of the diagram, whereas the pulses delivered directly by the digits 1 to 6 are shown in lines 46, to 46 The oscillator frequency is determined by the desired dura-- tion of the entire measurement period T and by the ratio of the interval during which the counter results are evaluated, to the interval r,, during which the counting takes place. The calculation is as follows:

During the evaluation interval a trailing flank of a pulse must be produced six times. We may therefore write:

5 T... Moreover:

T, r, Therejs therefore obtained, for the oscillator frequency:

' l/T..=(T,,T,.5) l/t In order to ensure that the rhythmic pulses l to 6 are effective only once during a run through of the frequency divider 46, that is to say only once during each measurement cycle, the leads 46, to 46 are connected to the A-input terminals of AND-gates 50 to 50 whose B inputs are connected in common to the output terminal 49a of an AND-gate 49. This AND-gate 49 has input terminals B, C, D, which are connected for example to the penultimate digits of the decades 46", 46" 46 which follow the decade 46, to the effect that the gates 50,, 50 etc. are able to open only if an output signal prevails on all the penultimate digits of the decades 46", 46", 46".

In order to ensure that the rhythmic pulses 1 to 6 act, over the

leads

46,, 46 etc., on the logic circuit 42 only when they have reached their highest values, and do not act while they are increasing or decreasing in intensity, which would involve a degree of uncertainty, a monovibrator 48 receives pulses from the output terminal of the rythmic oscillator 44. The output terminal of the monovibrator 48 is connected over a lead 48a to the input terminal A of the AND-gate 49. As will be seen from FIGS. 6a and 6b,.in line 48a, monovibrator pulses aretriggered by the leading flanks of the oscillator pulses, and their duration is somewhat less than an oscillator pulse. It should be observed that the lead 49a delivers a voltage sufficient for opening the gates 50,, 50 etc. only provided that the penultimate digits of the decades 46", 6 46 are carrying an output signal and also provided that the monovibrator 48 delivers a pulse. Consequently there occur on the output terminals of the AND-gates 50 50 50 etc. only the short rhythmic pulses, which are suitable for controlling the logical circuit 42, as represented in FIGS. 60 and 6b on lines 51 to 56.

The logic circuit, which is controlled by the rhythmic pulses S1, 52, 53, 54, 55, 56, has a first flip-flop 58, a second flip-flop 60, a negator 62, a third flip-flop 64, a fourth flip-flop 66, an ORgate 68, as well as the AND-gate 21b.

The first flip-flop 58 has an output terminal 74 which is connected to the B input terminal of the AND-gate 24 shown in FIG. 4. The flip-flop 60 has an output terminal 76, which is connected to the A input terminals of the AND-gate 26 shown in FIG. 4. The negator 62 has an output terminal 78 which is connected to the input terminals of the number setting switches 12', 12", etc. The output terminal of the third flipflop 64 is connected over the control lead 80 to the relay 34. The OR-gate 68 has an output lead 36 which is connected directly to the triggering input terminals of the flip-

flops

16, 16" shown in FIG. 4. The flip-flop 66 has a triggering input terminal which is connected to the lead m, that is to say to the output terminal Q of the last flip-flop of the highest decade counter 10' (not shown) of the counter 10, this flip-flop having a weighting 2 Let us assume that after a complete run through of the frequency divider 46 the transition has been reached from I, to t in FIG. 6a (no zero transition). The first rhythmic pulse 51 acting over the reset input terminal of the first flip-flop 58, ensures that the lead 74, which is connected to the output terminal of the flip-flop 58, assumes the state represented in line 74 in FIG. 6, so that the AND gate shown in FIG. 3 is blocked. This has the effect of interrupting the feed of measured value pulses to the input terminal 13 of the counter 12, as represented in FIG. 60 on line 13. The counter 10 therefore retains its existing state, that is to say it retains the state which it has at this instant. At the same time, over the lead 51, the reset input terminal of the second flip-flop 60 is influenced in such a way that the output terminal 6 of this flip-flop assumes the state represented on line 76 in FIG. 6, with the result that the gates 26 become conductive, establishing in this regard a connection between the input terminals J, K of the flip-flops 16', 16" and the corresponding output terminals of the decade counters l0, 10'. These bistable flip-flops function in such a way that the signals arriving at this instant over the AN D-gate 26 do not yet influence the states of the flip-flops 16, but merely remain on the signal input terminals J, K.

However the second rhythmic pulse, passing over the lead 52 and over the OR-gate 68, reaches the lead 36, which is connected to the triggering input terminals 17 of the bistable flipflops I6, 16'. As soon as this pulse arrives, as represented in FIG. 6 on line 36, the signals on the input terminals J an K act on the flip-

flops

16, 16", The behavior of the bistable flipflops is described in the table shown in FIG. 7. If before the arrival of the triggering pulse there prevails on the input terminal J the state zero, and on the input terminal K the state L, then, when the triggering pulse arrives, the output terminal Q will assume the value zero, irrespective of the previous state of one of the flip-flops 16', 16". On the other hand, if the signals on the input terminals J and K are arranged the opposite way round (J L), (K 0), then on the arrival of the triggering pulse the output terminal Q assumes the value L. This may be summarized by saying that the value on the output terminal Q of a flip-

flop

16, 16 is always exactly the same as the value Q on a counter l0, 10', etc. at the instant when the counter delivers a numerical value to the memory 16.

Furthermore, the second rhythmic pulse at the same time re-sets the third flip-flop 64, with the result that the output terminal Q of the flip-flop 64 changes over to the state L, as represented in FIG. 6 on line 80. This activates the relay 34, to the effect that the pole reverser 20 gives the signal leads 32a, 32b a polarity which, let us assume, is opposite to the polarity which would prevail if there had been no zero transition. However this is then immediately changed again by means of a fourth rythmic pulse, which has not yet been mentioned.

The third rhythmic pulse, passing over the lead 53, reaches the triggering input terminal of the second flip-flop 60, whose output terminal 6 returns to the state zero, so that the lead 76, that is to say the A input terminals of the AND-gate 26 acquire a potential which blocks the AND-gate 26. The effect of this is that the output terminals of the counter 10 are separated from the input terminals of the memory unit 16. Consequently all the input terminals J and K of the flip-flops I6, 16" etc. are now at the potential L, due to the negating action of the NAND-gates 26.

In the case represented in FIG. 6a, which assumes that no zero transition has occurred, the output 6 of the flip-flop 66 delivers, over the lead 66a, a potential such that the AND-gate 21b remains open, with the result that the leading flank of the fourth rhythmic pulse, passing over the gate 21b and over the OR-gate 68, reaches the lead 36, and also reaches the input terminal of the third flip-flop 64. Consequently the fourth rhythmic pulse, passing over the lead 36, inverts the states of the output terminals Q of the flip-flop 16, as indicated in the table shown in FIG. 7, because all the input terminals J and K of the flip-

flops

16, 16" are at the potential L, due to the negating action of the NAND-gate 26. At the same instant a pulse, passing over the negator 62 and over the lead 78, reaches the number setting switches l2, 12'', as represented in FIG. 6 on line 78. This pulse ensures that the

counters

10, 10" etc. are reset to the desired value. The arrival of the pulse on the input terminal of the flip-flop 64 returns its output terminal Q to the state zero, with the result that the pole reverser 20 is changed over into the position which corresponds to no zero transition having taken place.

The fifth rhythmic pulse reaches the reset input terminal of the fourth flip-flop 66, so that its output terminal 0 in all cases assumes the potential L, preparing the AND-gate 21 to open even if a signal indicating a zero transition has previously reached the triggering input terminal over the lead 10m".

Finally, on the arrival of the sixth rhythmic pulse, the input terminal of the first flip-flop 58 is activated, with the result that its output terminal Q once more acquires the potential L, as represented in FIG. 6 on line 74. As will be seen from line 13 in FIG. 6, during a further time interval 2, a new sequence of pulses can now be fed into the counter.

In describing the process on the basis of FIG. 60, it was assumed as the initial situation that no zero transition had taken place, as represented in the diagram of FIG. 3a. On the other hand FIG. 6b represents the process based on the assumption that during the counting process the counter 10 passed through its zero position, as represented in FIG. 3b. During the interval of time 1,, as represented in FIG. 6b, the zero transition is indicated at the point A on line 10m". In order to determine whether a zero transition has taken place or not, the procedure is as follows. Referring to FIG. 2, in the fourth flip-flop in each of the

individual decades

10, 10" etc. a changeover from L to zero occurs only once during each run through. It follows that if the last digit of the fourth decade 10" of the counter changes over from L to zero, this must be because the counter 10 has passed through its zero position. A pulse corresponding to this change over can therefore pass over the lead 10m and reach the input terminal of the fourth flip-flop 66, which can therefore be used to give an indication that zero transition has taken place. This flip-flop 66 functions as the discriminator indicated at 22 in FIG. 1.

Under these circumstances the output lead 66a acquires the output potential zero, as represented in FIG. 6 on line 66a, with the result that the AND-gate 21b is blocked. The fourth flip-flop 66 remains in this state until subsequently the fifth rhythmic pulse, passing over the lead 55 and the reset input terminal of the flip-flop 66, returns the output terminal 6 to the potential L, as represented in FIG. 6, on line 66a. This blocking of the gate 21b prevents the fourth rhythmic pulse from passing over the lead 36 to the triggering inputs of the flip-flops 16, as was indicated in FIG. 6a, so that under these circumstances no inversion occurs. Furthermore the fourth rhythmic pulse does in this case not influence the state of the third flip-flop 64, and consequently the polarity change in the pole reverser 20, which was effected by the trailing flank of the second rhythmic pulse, remains sustained and is not cancelled out again by the fourth rhythmic pulse, as it was in the example described on the basis of FIG. 6a.

What is obtained in this way is that at remarkably low cost in apparatus, and using only a single counter which always counts forwards, and without any occurrence of coincidence effects, and moreover with great reliability in handling both positive and negative deviations between the measured value and the desired value, an apparatus can be constructed capable of delivering control signals, each time with the correct mathematical sign, in such a way that the value of the deviation can be displayed with the degree of accuracy attainable by digital methods, this degree of accuracy depending essentially on the number of digits used and on the number of pulses received.

We claim:

1. A circuit for carrying out a method of continuously evaluating deviations between the measured value and the desired value of a quantity represented by a sequence of pulses, comprising a counter having an input terminal and output terminals and constructed of bistable flip-flops, a number setting switch connected to the counter for pre-setting the counter to the complement of the Aiken Coded desired value, a first AND gate which can be blocked during a second time interval, a lead for conveying the sequence of measured value pulses to the counter, means connecting the input terminal of the counter to said lead via the first AND gate, a plurality of NAND gates having A and B input terminals and output terminals, means connecting the output terminals of the counter to the B input terminals of the NAND gates, a memory having signal input terminals and comprising additional bistable flipflops having input terminals and triggering input terminals, a pulse lead for carrying a potential, means connecting the A input terminals of the NAND gates to the pulse lead during a part of a second time interval suitable for opening the NAND gates so that the number stored in the counter reaches the input terminals of the flip-flops of the memory, a lead conveying triggering pulses, and means connecting the triggering input terminals of the flip-flops of the memory to the lead conveying triggering pulses.

2. A circuit as claimed in claim 1, further comprising a logic circuit connected to the counter for controlling the counter to give correct timing, and a rhythmic pulse generator connected to the logic circuit. 3. A circuit as claimed in claim 2, wherein the rhythmic pulse generator comprises a frequency stable oscillator and a counter consisting of decades and functioning as a frequency counter, said frequency counter being connected to and fed by the frequency stable oscillator and having outputs producing rhythmic pulses which control the logic circuit.

4. A circuit as claimed in claim 3, wherein the logic circuit includes a first flip-flop having a reset input terminal receiving the first rhythmic pulse, a triggering input terminal receiving the sixth rhythmic pulse and an output terminal connected by a lead to an input terminal of the first AND gate; a second flipflop having a reset input terminal receiving the first rhythmic pulse, a triggering input terminal receiving the third rhythmic pulse and an output terminal connected by a lead to the A input terminals of the NAND gates; a negator having an input receiving the fourth rhythmic pulse of the pulse generator, and an output terminal connected to the input of the number setting switch; a second AND gate having A and B input terminals and an output terminal; a pole reverser; a third flip-flop having a reset input receiving the second rhythmic pulse, a triggering input terminal receiving the fourth pulse via the second AND gate, and an output terminal connected to the pole reverser; an OR gate having an A input terminal receiving the second rhythmic pulse, a B input terminal connected to the output terminal of the second AND gate, and an output terminal connected by a lead to the triggering input terminal of the memory; and a fourth flip-flop having a reset terminal receiving the fifth rhythmic pulse, a triggering input terminal connected to an output terminal, which represents the zero transition of the counter, of the last decade of the counter, and an output terminal connected to the B input terminal of the second AND gate.

5. A circuit as claimed in claim 4, wherein the logic circuit further comprises a third AND gate having A, B, C and D input terminals and an output and additional AND gates having A and B input terminals, and wherein the decade counters of the frequency divider have pluralities of inputs and outputs and with the exception of the first decade, the penultimate output terminals of the decade counters of the frequency divider are each connected to the B, C and D input terminals, respectively, of the third AND gate, the output terminal of the third AND gate is connected to the B input terminals of the additional AND gates, and the A input terminals of the additional AND gates are connected to the first to sixth input terminals of the first decade counter.

6. A circuit as claimed in claim 5, wherein the logic circuit further comprises a monostable multivibrator having a switching time less than the duration of a pulse delivered by the frequency stable oscillator of the pulse generator and an output terminal connected to the A input terminal of the third AND gate, and wherein the frequency stable oscillator has an output terminal connected to the input terminal of the monostable multivibrator.

7. A circuit as claimed in claim3, wherein the frequency of the frequency stable oscillator is expressed by the equation l/T,= (T,,/I,,5) l/t wherein T, is one-fifth of the time interval r, during which the counter results are evaluated, 1, is the time interval during which the counting takes place, and T is the entire measurement period of z, t

8. A circuit as claimed in claim 7, wherein said logic circuit comprises a pole reversing switch for changing over from one polarity position to another and a line providing an initial pulse, said switch comprising a relay having a coil excited and unexcited via the line in dependence on an initial pulse, the relay changing the switch over from one polarity position to the other.

9. A circuit as claimed in claim 8, further comprising a digital to analog converter having an output terminal connected to the switch, and wherein the memory has output terminals connected to the digital to analog converter.

Claims

1. A circuit for carrying out a method of continuously evaluating deviations between the measured value and the desired value of a quantity represented by a sequence of pulses, comprising a counter having an input terminal and output terminals and constructed of bistable flip-flops, a number setting switch connected to the counter for pre-setting the counter to the complement of the Aiken Coded desired value, a first AND gate which can be blocked during a second time interval, a lead for conveying the sequence of measured value pulses to the counter, means connecting the input terminal of the counter to said lead via the first AND gate, a plurality of NAND gates having A and B input terminals and output terminals, means connecting the output terminals of the counter to the B input terminals of the NAND gates, a memory having signal input terminals and comprising additional bistable flip-flops having input terminals and triggering input terminals, a pulse lead for carrying a potential, means connecting the A input terminals of the NAND gates to the pulse lead during a part of a second time interval suitable for opening the NAND gates so that the number stored in the counter reaches the input terminals of the flipflops of the memory, a lead conveying triggering pulses, and means connecting the triggering input terminals of the flip-flops of the memory to the lead conveying triggering pulses.

2. A circuit as claimed in claim 1, further comprising a logic circuit connected to the counter for controlling the counter to give correct timing, and a rhythmic pulse generator connected to the logic circuit.

3. A circuit as claimed in claim 2, wherein the rhythmic pulse generator comprises a frequency stable oscillator and a counter consisting of decades and functioning as a frequency counter, said frequency counter being connected to and fed by the frequency stable oscillator and having outputs producing rhythmic pulses which control the logic circuit.

4. A circuit as claimed in claim 3, wherein the logic circuit includes a first flip-flop having a reset input terminal receiving the first rhythmic pulse, a triggering input terminal receiving the sixth rhythmic pulse and an output terminal connected by a lead to an input terminal of the first AND gate; a second flip-flop having a reset input terminal receiving the first rhythmic pulse, a triggering input terminal receiving the third rHythmic pulse and an output terminal connected by a lead to the A input terminals of the NAND gates; a negator having an input receiving the fourth rhythmic pulse of the pulse generator, and an output terminal connected to the input of the number setting switch; a second AND gate having A and B input terminals and an output terminal; a pole reverser; a third flip-flop having a reset input receiving the second rhythmic pulse, a triggering input terminal receiving the fourth pulse via the second AND gate, and an output terminal connected to the pole reverser; an OR gate having an A input terminal receiving the second rhythmic pulse, a B input terminal connected to the output terminal of the second AND gate, and an output terminal connected by a lead to the triggering input terminal of the memory; and a fourth flip-flop having a reset terminal receiving the fifth rhythmic pulse, a triggering input terminal connected to an output terminal, which represents the zero transition of the counter, of the last decade of the counter, and an output terminal connected to the B input terminal of the second AND gate.

7. A circuit as claimed in claim 3, wherein the frequency of the frequency stable oscillator is expressed by the equation 1/Te (Ta/Te - 5) 1/t1 wherein Te is one-fifth of the time interval t2 during which the counter results are evaluated, t1 is the time interval during which the counting takes place, and Ta is the entire measurement period of t1 + t2.