CA1216954A - Word store equipped with an address code conversion circuit - Google Patents
Word store equipped with an address code conversion circuitInfo
- Publication number
- CA1216954A CA1216954A CA000446408A CA446408A CA1216954A CA 1216954 A CA1216954 A CA 1216954A CA 000446408 A CA000446408 A CA 000446408A CA 446408 A CA446408 A CA 446408A CA 1216954 A CA1216954 A CA 1216954A
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- bits
- multiplexer
- significant
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
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- Microelectronics & Electronic Packaging (AREA)
- Time-Division Multiplex Systems (AREA)
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Abstract
ABSTRACT OF THE DISCLOSURE
Word store equipped with an address code conversion circuit making it possible to obtain AxB words, A and B not being powers of two.
The code conversion circuit is in two parts CTA(X) and CTA(Y), allocated respectively to the code conversion of two addresses X and Y. The first part CTA(X) comprises a multiplexer M(X), which multiplexes the r most significant bits of X with the determined logic level. The second part CTA(Y) comprises a multiplexer M(Y), which multiplexes the r most significant bits of Y (with the exception of the most significant bit) with the r most significant bits of X. The multi-plexers are controlled by the most significant bit of one of the addresses.
Application to the formation of stores, particularly for graphic or alphanumeric display screens.
(Fig. 2)
Word store equipped with an address code conversion circuit making it possible to obtain AxB words, A and B not being powers of two.
The code conversion circuit is in two parts CTA(X) and CTA(Y), allocated respectively to the code conversion of two addresses X and Y. The first part CTA(X) comprises a multiplexer M(X), which multiplexes the r most significant bits of X with the determined logic level. The second part CTA(Y) comprises a multiplexer M(Y), which multiplexes the r most significant bits of Y (with the exception of the most significant bit) with the r most significant bits of X. The multi-plexers are controlled by the most significant bit of one of the addresses.
Application to the formation of stores, particularly for graphic or alphanumeric display screens.
(Fig. 2)
Description
WORD STORE EQUIPPED WITH AN ADDRESS
CODE CONVERSION CIRCUIT
, BACKGROUND OF THE INVENTION
, Existing stores or memories are organized into words constituted by several bits. The number of words is generally a power of two.
As there is often a need for stores having a matrix form, the distrlbution of these words corresponds to matrixes of 2P by 2q words.
In this case, for reading or writing a word in the store, it ismerely necessary to display a column address X on a first group of p address wires and a row address Y on a second group of q address wires.
However, it is sometimes desirable to have a store of AxB words, in which the numbers A
and B are not powers of two. This is particular-ly the case with alphanumeric screen memories, where is a need for 80x24 characters (or 80x25) or graphic screen memories with a facsimile format with 1728x2288 points in which the points are grouped in words of 64 bits, which leads to 27x2288 word memories.
When A and B are not powers of two, it is possible to write:
2P < A ~ 2P (1) 2q < B ~ 2q p and q being exponents of the closest powers of 2 below A and B.
In other words, this means that A is expressed by p+l bits ard B by q+l bits. Two cases can occur:
B 77~i0 C/RS
if 2P q S Ax~ < 2p+q+2 (2) it is necessary to use a memory with 2p+q+2 words and it is then necessary merely to respectively increase A and B by 2P+1 and 2q+1 if 2P q < AxB ~ 2P q+1 (3) it is also possible to use a memory with 2p+q+2 words, but it would be poorly used, because the half between 2p+q+l and 2 p+q+2 would be unused.
SUMMARY OF THE INVENTION
The problem to be solved by the invention is to find a means making it possible to use a memory with a capacity of 2P+q 1 words, in the special case where each word is de*ined by a first address with p+1 bits and a second address with q+1 bits.
The invention solves this problem by adding an address code conversion circuit with p+q+2 inputs and p+q+1 outputs. This circuit comprises two parts:
a. a first part constituted by:
- p+1 inputs and p-~1 outputs, the p+1 inputs receiving p+1 bits defining a number X
lower than A, said bits being distributed between a least significant bit and a most significant bit, the p+1 outputs being connected to p+1 first addressing inputs of the memory or store, 0 - p+1-r direct connections between the p+1-r inputs allocated to the p+1-r least signifi-cant bits and p+1-r outputs, - a first multiplexer having a first group of .1., . .~
r inputs receiving logic expressions of the r most significant bits of X received by the r corresponding inputs, and having a second group of r inputs raised to the same predetermined logic level, said first multiplexer having r outputs connected to the r remaining outputs of said first part, b. a second part constituted by:
- q~l inputs and q outputs, the q+l inputs receiving the q+l bits defining a number Y
lower than B, said bits being distributed between a most significant bit and a least significant bit, the q outputs being connected to the q final addressing inputs of the memory, - q-r direct connections between the q-r inputs allocated to the q-r least signifi-cant bits of Y and q~r outputs, - a second multiplexer having a first group of r inputs receiving logic expressions of r most significant bits of Y taken after the most significant bit of Y and having a second group of r inputs connected to the first group of r inputs of the first multiplexer of the first part, said second multiplexer having r outputs connected to the r remaining outputs of said second part, each multiplexer also having a control input receiving the most significant bit of number Y
applied to the most significant input of the second part.
s~
Hereinbefore, r is an integer proving the relations:
_l) 2p+1-r ~ A
(4) 2q ~ 2q-r ~ B
As a result of this code conversion circuit, the r addressing inputs of the memory which are connected to the outputs of the first multiplexer receive, in accordance with the value of the most significant bit of Y, either r logic expressions of r most significant bits of X, or r predetermined logic levels, the r addressing inputs of the memory which are connected to the inputs of the second multiplexer receiving in the same way either the r most significant bits of Y taken after the most significant bit, or the r most significant bits of X. Thus, address multiplexing takes place on two groups of r addressing inpu-ts.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is described in greater detail hereinafter relative to non-limitative embodiments and the attached drawings, wherein show:
Fig. 1 a diagram showing the respective position of numbers A and B relative to the powers of two.
Fig. 2 a general diagram of a store according to the invention.
Fig. 3 a special embodiment of a 24x80 word store using 2048 word store.
Fig. 4 a special embodiment of a 27x2288 word store using a 64K word store.
.r~s~
DETAILED DESCRIPTION OF THE INVENTION
Fig. 1 is a diagram graphically showing the relative posi-tions of numbers A and B and the product AB. The latter is assumed to be between 2P+q and 2P+q 1 and not between 2P q+ and 2P q+2, in which case the only means available would be to use a store having a capacity of 2p+q+2. Thus, the sphere of application of the invention corresponds to the hached area of the axis.
The idea on which the invention is based is to multiplex certain addresses for reduci~g from p+q+2 to p+q+l the number of addressing inputs. This multiplexing is possible by carefully using two groups of r addresses, the number r being defined on the basis of two numbers A' and B' equal to or exceeding A + B, respectively:
A' = 2P+1 r (2r~ A
(4) B' 2q-r (2r+1) B
As the number A' is equal to 2P+1-2P+l r, it is consequently lower than 2P 1. As the number B' is equal to 2q-~2q r, it is less than 29+2q, i.e. to 2q+l. The product A'B' is equal to 2P+q+l-2P+q 1 r. It is consequently between AB and 2P q 1. In other words, a memory with A'B' words falls within the scope of the invention and has a capacity exceeding AB. The respective positions of A', B' and A'B' are indicated in the diagram of Fig. 1. Point A'B' is within the h~ched area.
Instead of producing a memory of AB
words3 a memory of A'B' words will be produced by using the special form of the product A'B'.
When the most significant bit of Y is at 1, which gives Y at least the value 2q, all the bits of Y with a significance exceeding q-r are necessarily zero, otherwise B' would exceed 2q+2q r. This makes it possible to multiplex the addresses in -the following manner:
- p+1-r addressing inputs permanently receive p+1-r least significant bits of the number X below A, - q-r addressing inputs permanently receive the q-r least significant bits of the number Y lower than B, - r addressing inputs either receive the r most significant bits of X when the most significant bit of Y is at zero, or "1"
(i.e. a predetermined logic level) when the most significant bit of Y is at "1", - r other addressing inputs receive either the r most significant bits of Y (except its most significant bit) when the most significant bit of Y is at "0", or the r most significant bits of X when the mos-t significant bit of Y is at "1".
To define these questions, the p+1 bits of X should be designated Xo ... Xp (Xo designating the least significant bit and Xp the most significant bit). In the same way the q+1 bits of Y are designated Yo ... Yq (Yo being the most significant bit and Yq the least significant bit). Finally, the p+q+l addressing inputs of the store are designated Mo ... Mp+q.
It is therefore possible to write the 5 correspondence between the addressing inputs and the addressing bits in the following way:
r q-r r p+1-r on: ~ ~ ~ ~
if Yq=0 we find Yq-l.. Yq-r Yq~r-1u... Yo Xp... Xp+1-r Xp-r.. Xo 10 if Yq=1 we find Xp...... Xp+1-r Yq-r-l.. Yo "1".. .."1" ~p-r... Xo ~......... 1' 1`................ ~
me multiplexed inputs are designated by arrows.
In order to find the integer r, it is necessary to start with the inequations (4) 15 and the smallest power of two exceeding B-2q is sought, which will give 2q r. From this is deduced the highest possible value of r and it is established whether the value satisfies the first inequation of inequations (4), relative to A, namely (2r_1) 2P+1-r A.
If r exists, it can have several appropriate values and in this case the smallest value is preferably chosen. If r does not exist, the test is repeated by permutating A and B.
From a specific standpoint, a store designed according to the invention is in the form illu-strated in Fig. 2~ The actual store or MEM
comprises p+q+1 addressing inputs Mo to Mp+q.
It is preceded by an address code conversion circuit CTA in two parts, respectively CTA (A) and CTA(Y), which process the numbers X and Y
constituting the addresses of the word to be designated from the AxB possible words.
5~
The first part CTA(X) is constituted by:
- p+1 inputs E(X)o...E(X)p and p+1 outputs designated S(X)o...S(X)p, the p+1 inputs receiving the P+1 bits Xo, Xl...Xp defining -the number X, said bits being distributed between a least significant bit Xo and a most significant bit, the p+1 outputs being connected to p+1 first addressing inputs of the memory, i.e. Mo to Mp;
10 - p+1-r direct connections CD(X) between the p+1-r inputs E(X)o...E(X)p-r allocated to the p+1-r least significant bits Xo...Xp-r and p+1-r outputs S(X)o...S(X)p-r;
- a first multiplexer M(X) having a first group e(X)1 of r inputs receiving the logic expressions of r most significant bits of X (Xp-r+l...Xp) received by the r correspond-ing inputs E(X)p-r+l...E(X)p, the multiplexer having a second group E(x)2 of r inputs raised to the same predetermined logic level, e.g. 1, said first multiplexer finally having r outputs r s(X) connected to the r remaining outputs S(X)p-r+l...S(X)p.
The second par-t CTA(Y) of the code conversion circuit is constituted by:
- q+1 inputs E(Y)o...E(Y)q and q outputs S(Y)o...S(Y)q-1, the q+1 inputs receiving q+1 bits, namely Yo, Yl,...Yq defining the number Y, said bits being distributed between a least significant bit Yo and a most signifi-cant bit Yq, the q outputs S(Y)o.O.S(Y)q-1 being connected to the q final addressing ~6~
inputs of the memory, namely Mp+l...Mp+q;
- q-r direct connections CD(Y) between the q-r inputs E(Y)o...E(Y)q-r allocated to the q-r least significant bits Y and q-r outputs S(Y)o.. S(Y)q-r-l;
- a second multiplexer M(Y) having a first group e(X)l of r inputs receiving the logic expressions of the r most significant bits Yq-r...Yq-l of Y taken after the most significant bit Yq and a second group e(Y)2 of r inputs connected to the first group of r inuts of the first multiplexer of the first part, said second multiplexer having r outputs s(Y) connected to the r remaining outputs of said second part, namely S(Y)q-r...S(Y)q-l.
Each multiplexer M(X), M(Y) also has a control input, respective]y C(X), C(Y), which receives a logic expression of the most significant bit of the number Y, namely Yq, applied to the most significant input E(Y)q of the second part.
The r addressing inputs MP r+l...Mp of the store connected to the outputs of the first multiplexer M(X) consequently receive, as a function of the value of the most significant bit Yqof Y, r logic expressions of the r most significant bits of X, or r predetermined logic levels. In the same way, the r addressing inputs Mp+q-r...Mp+q of the store, which are connected to the outputs of the second multiplexer, receive either the r most significant bits of Y taken after Yq, or the r most significant bits of X.
~i.6~
Apart from its addressing inputs, the memory MEM naturally has a control input 10 connected to a control bus 12 and a data input 14 connected to a data bus 16.
In the preceding description, the inputs of the multiplexers receive certain bits, but they could obviously also receive their complement. In this case it would merely be necessary to add to the represented circuit, a logic inverter between the code conversion circuit input and the multiplexer input. In the following examples, it is assumed that the inputs of the multiplexers receive the actual bits~
In practice ? each multiplexer is constituted by r elementary multiplexers having two inputs and an output. For example it is possible to use the multiplexer 74-LS 158 of Texas Instru-ments.
Two embodiments will now be described relative to Figs. 3 and 4.
The first embodiment corresponds to an alphanumeric display screen memory with 80x24 words using a 2048 word memory. With the pre-ceding notations, we have p=6 and q=4, as well as A=80 and B=24.
The relations defining r are then:
A' (2r l)x 26+1-r ~ 80 and B' 24 + 24-r ~ 24 The second inequation imposes 2 ~ 24-16, i.e. 24 r ~ 8, thus r=1. Consequently A'=64.
As A' does not exceed A, this solution is not suitable.
~L~
The test is repeated by permutating the two numbers A and B. Thus, on this occasion we take p=4 and q=6 with A=24 and B=80.
r is sought such that:
A~ = (2r-1) x 24+1 r ~ 24, and B' 26 + 26-r ~ 80 The second inequation gives 2 r 80-64=16 9 namely r=2. This means that A'=24, which is suitable. The solution is therefore p=4, q=6, r=2.
The multiplexing diagram is as follows and the multiplexed wires are again marked by an arrow:
M10 M9 M8 M7 M~ M5 M4 M3 M2 Ml M0 15 Y6=0: Y5 Y4 Y3 Y2 Y1 Y0 X4 X3 X2 Xl X0 Y6=1: X4 X3 Y3 Y2 Y1 Y0 "1" "1" X2 Xl X0 Thus, a memory circuit with 24 x 80 words is obtained and is shown in Fig. 3. It comprises a first multiplexer M(X) constituted by two multiplexers 2 ~ 1, respectively M(X)1 and M(X)2 whereof the inputs receive X3 and X4 on the one hand and two logic signals on the other. It oomprises a second multiplexer M(Y), which is also constituted by two multiplexers 2 ~ 1, respectively M(Y)1 and M(Y)2, whose inputs receive Y4, Y5 on the one hand and X3, X4 on the other. The most significant bit Y6 controls both of them. The memory MEM has 11 addressing inputs M0 to M10. The code conversion circuit CTA has five inputs for address X, namely X0 to X4, six inputs for address Y, namely Y0 to Y5 6~
plus the control inputs Y6 and ele~ren outputs S(X)O to S(X)4 and S(Y)O to S(Y)5.
The second embodiment corresponds to a graphic display screen memory with 27x2288 words using a 64k word memory. In this embodiment, we have p=4 and q=11 as well as A=27 and B=2288.
r is sought such that:
A' = (2 -1) X 2 1 r 27, and B' = 211 + 211-r 2288 The second inequation gives r=3, hence A' = 28, this solution being suitable. Thus, the following multiplexing diagram is obtained:
M~5 M14 M13 MU2 Mll M~0 M9 M8 M7 M6 M5 M4 M3 M2 Ml MD
if Yll=0 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Yl Y0 X4 X3 X2 Xl X0 if Yll=l X4 X3 X2 Y7 Y6 Y5 Y4 Y3 Y2 Yl Y0 "1" "1" "1" Xl X0 In this way, we obtain a memory with 28x2304 words, namely 1792x2304 points. Each word can consist of 64 bits in the case of the graphic display application. Fig. 4 shows the circuit obtained.
The address code conversion circuit has five inputs allocated to X (XO to X4) and twelve inputs allocated to Y (YO to Y11). The multi-plexers M(X) and M(Y) each comprise three multiplexers 2 ~ 1. The first multiplexer elements X2, X3, X4 with the same logic level "l' and the second multiplexer elements Y8, Y9, Y10 with X2, X3, X4. The multiplexing control is provided by Y11.
CODE CONVERSION CIRCUIT
, BACKGROUND OF THE INVENTION
, Existing stores or memories are organized into words constituted by several bits. The number of words is generally a power of two.
As there is often a need for stores having a matrix form, the distrlbution of these words corresponds to matrixes of 2P by 2q words.
In this case, for reading or writing a word in the store, it ismerely necessary to display a column address X on a first group of p address wires and a row address Y on a second group of q address wires.
However, it is sometimes desirable to have a store of AxB words, in which the numbers A
and B are not powers of two. This is particular-ly the case with alphanumeric screen memories, where is a need for 80x24 characters (or 80x25) or graphic screen memories with a facsimile format with 1728x2288 points in which the points are grouped in words of 64 bits, which leads to 27x2288 word memories.
When A and B are not powers of two, it is possible to write:
2P < A ~ 2P (1) 2q < B ~ 2q p and q being exponents of the closest powers of 2 below A and B.
In other words, this means that A is expressed by p+l bits ard B by q+l bits. Two cases can occur:
B 77~i0 C/RS
if 2P q S Ax~ < 2p+q+2 (2) it is necessary to use a memory with 2p+q+2 words and it is then necessary merely to respectively increase A and B by 2P+1 and 2q+1 if 2P q < AxB ~ 2P q+1 (3) it is also possible to use a memory with 2p+q+2 words, but it would be poorly used, because the half between 2p+q+l and 2 p+q+2 would be unused.
SUMMARY OF THE INVENTION
The problem to be solved by the invention is to find a means making it possible to use a memory with a capacity of 2P+q 1 words, in the special case where each word is de*ined by a first address with p+1 bits and a second address with q+1 bits.
The invention solves this problem by adding an address code conversion circuit with p+q+2 inputs and p+q+1 outputs. This circuit comprises two parts:
a. a first part constituted by:
- p+1 inputs and p-~1 outputs, the p+1 inputs receiving p+1 bits defining a number X
lower than A, said bits being distributed between a least significant bit and a most significant bit, the p+1 outputs being connected to p+1 first addressing inputs of the memory or store, 0 - p+1-r direct connections between the p+1-r inputs allocated to the p+1-r least signifi-cant bits and p+1-r outputs, - a first multiplexer having a first group of .1., . .~
r inputs receiving logic expressions of the r most significant bits of X received by the r corresponding inputs, and having a second group of r inputs raised to the same predetermined logic level, said first multiplexer having r outputs connected to the r remaining outputs of said first part, b. a second part constituted by:
- q~l inputs and q outputs, the q+l inputs receiving the q+l bits defining a number Y
lower than B, said bits being distributed between a most significant bit and a least significant bit, the q outputs being connected to the q final addressing inputs of the memory, - q-r direct connections between the q-r inputs allocated to the q-r least signifi-cant bits of Y and q~r outputs, - a second multiplexer having a first group of r inputs receiving logic expressions of r most significant bits of Y taken after the most significant bit of Y and having a second group of r inputs connected to the first group of r inputs of the first multiplexer of the first part, said second multiplexer having r outputs connected to the r remaining outputs of said second part, each multiplexer also having a control input receiving the most significant bit of number Y
applied to the most significant input of the second part.
s~
Hereinbefore, r is an integer proving the relations:
_l) 2p+1-r ~ A
(4) 2q ~ 2q-r ~ B
As a result of this code conversion circuit, the r addressing inputs of the memory which are connected to the outputs of the first multiplexer receive, in accordance with the value of the most significant bit of Y, either r logic expressions of r most significant bits of X, or r predetermined logic levels, the r addressing inputs of the memory which are connected to the inputs of the second multiplexer receiving in the same way either the r most significant bits of Y taken after the most significant bit, or the r most significant bits of X. Thus, address multiplexing takes place on two groups of r addressing inpu-ts.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is described in greater detail hereinafter relative to non-limitative embodiments and the attached drawings, wherein show:
Fig. 1 a diagram showing the respective position of numbers A and B relative to the powers of two.
Fig. 2 a general diagram of a store according to the invention.
Fig. 3 a special embodiment of a 24x80 word store using 2048 word store.
Fig. 4 a special embodiment of a 27x2288 word store using a 64K word store.
.r~s~
DETAILED DESCRIPTION OF THE INVENTION
Fig. 1 is a diagram graphically showing the relative posi-tions of numbers A and B and the product AB. The latter is assumed to be between 2P+q and 2P+q 1 and not between 2P q+ and 2P q+2, in which case the only means available would be to use a store having a capacity of 2p+q+2. Thus, the sphere of application of the invention corresponds to the hached area of the axis.
The idea on which the invention is based is to multiplex certain addresses for reduci~g from p+q+2 to p+q+l the number of addressing inputs. This multiplexing is possible by carefully using two groups of r addresses, the number r being defined on the basis of two numbers A' and B' equal to or exceeding A + B, respectively:
A' = 2P+1 r (2r~ A
(4) B' 2q-r (2r+1) B
As the number A' is equal to 2P+1-2P+l r, it is consequently lower than 2P 1. As the number B' is equal to 2q-~2q r, it is less than 29+2q, i.e. to 2q+l. The product A'B' is equal to 2P+q+l-2P+q 1 r. It is consequently between AB and 2P q 1. In other words, a memory with A'B' words falls within the scope of the invention and has a capacity exceeding AB. The respective positions of A', B' and A'B' are indicated in the diagram of Fig. 1. Point A'B' is within the h~ched area.
Instead of producing a memory of AB
words3 a memory of A'B' words will be produced by using the special form of the product A'B'.
When the most significant bit of Y is at 1, which gives Y at least the value 2q, all the bits of Y with a significance exceeding q-r are necessarily zero, otherwise B' would exceed 2q+2q r. This makes it possible to multiplex the addresses in -the following manner:
- p+1-r addressing inputs permanently receive p+1-r least significant bits of the number X below A, - q-r addressing inputs permanently receive the q-r least significant bits of the number Y lower than B, - r addressing inputs either receive the r most significant bits of X when the most significant bit of Y is at zero, or "1"
(i.e. a predetermined logic level) when the most significant bit of Y is at "1", - r other addressing inputs receive either the r most significant bits of Y (except its most significant bit) when the most significant bit of Y is at "0", or the r most significant bits of X when the mos-t significant bit of Y is at "1".
To define these questions, the p+1 bits of X should be designated Xo ... Xp (Xo designating the least significant bit and Xp the most significant bit). In the same way the q+1 bits of Y are designated Yo ... Yq (Yo being the most significant bit and Yq the least significant bit). Finally, the p+q+l addressing inputs of the store are designated Mo ... Mp+q.
It is therefore possible to write the 5 correspondence between the addressing inputs and the addressing bits in the following way:
r q-r r p+1-r on: ~ ~ ~ ~
if Yq=0 we find Yq-l.. Yq-r Yq~r-1u... Yo Xp... Xp+1-r Xp-r.. Xo 10 if Yq=1 we find Xp...... Xp+1-r Yq-r-l.. Yo "1".. .."1" ~p-r... Xo ~......... 1' 1`................ ~
me multiplexed inputs are designated by arrows.
In order to find the integer r, it is necessary to start with the inequations (4) 15 and the smallest power of two exceeding B-2q is sought, which will give 2q r. From this is deduced the highest possible value of r and it is established whether the value satisfies the first inequation of inequations (4), relative to A, namely (2r_1) 2P+1-r A.
If r exists, it can have several appropriate values and in this case the smallest value is preferably chosen. If r does not exist, the test is repeated by permutating A and B.
From a specific standpoint, a store designed according to the invention is in the form illu-strated in Fig. 2~ The actual store or MEM
comprises p+q+1 addressing inputs Mo to Mp+q.
It is preceded by an address code conversion circuit CTA in two parts, respectively CTA (A) and CTA(Y), which process the numbers X and Y
constituting the addresses of the word to be designated from the AxB possible words.
5~
The first part CTA(X) is constituted by:
- p+1 inputs E(X)o...E(X)p and p+1 outputs designated S(X)o...S(X)p, the p+1 inputs receiving the P+1 bits Xo, Xl...Xp defining -the number X, said bits being distributed between a least significant bit Xo and a most significant bit, the p+1 outputs being connected to p+1 first addressing inputs of the memory, i.e. Mo to Mp;
10 - p+1-r direct connections CD(X) between the p+1-r inputs E(X)o...E(X)p-r allocated to the p+1-r least significant bits Xo...Xp-r and p+1-r outputs S(X)o...S(X)p-r;
- a first multiplexer M(X) having a first group e(X)1 of r inputs receiving the logic expressions of r most significant bits of X (Xp-r+l...Xp) received by the r correspond-ing inputs E(X)p-r+l...E(X)p, the multiplexer having a second group E(x)2 of r inputs raised to the same predetermined logic level, e.g. 1, said first multiplexer finally having r outputs r s(X) connected to the r remaining outputs S(X)p-r+l...S(X)p.
The second par-t CTA(Y) of the code conversion circuit is constituted by:
- q+1 inputs E(Y)o...E(Y)q and q outputs S(Y)o...S(Y)q-1, the q+1 inputs receiving q+1 bits, namely Yo, Yl,...Yq defining the number Y, said bits being distributed between a least significant bit Yo and a most signifi-cant bit Yq, the q outputs S(Y)o.O.S(Y)q-1 being connected to the q final addressing ~6~
inputs of the memory, namely Mp+l...Mp+q;
- q-r direct connections CD(Y) between the q-r inputs E(Y)o...E(Y)q-r allocated to the q-r least significant bits Y and q-r outputs S(Y)o.. S(Y)q-r-l;
- a second multiplexer M(Y) having a first group e(X)l of r inputs receiving the logic expressions of the r most significant bits Yq-r...Yq-l of Y taken after the most significant bit Yq and a second group e(Y)2 of r inputs connected to the first group of r inuts of the first multiplexer of the first part, said second multiplexer having r outputs s(Y) connected to the r remaining outputs of said second part, namely S(Y)q-r...S(Y)q-l.
Each multiplexer M(X), M(Y) also has a control input, respective]y C(X), C(Y), which receives a logic expression of the most significant bit of the number Y, namely Yq, applied to the most significant input E(Y)q of the second part.
The r addressing inputs MP r+l...Mp of the store connected to the outputs of the first multiplexer M(X) consequently receive, as a function of the value of the most significant bit Yqof Y, r logic expressions of the r most significant bits of X, or r predetermined logic levels. In the same way, the r addressing inputs Mp+q-r...Mp+q of the store, which are connected to the outputs of the second multiplexer, receive either the r most significant bits of Y taken after Yq, or the r most significant bits of X.
~i.6~
Apart from its addressing inputs, the memory MEM naturally has a control input 10 connected to a control bus 12 and a data input 14 connected to a data bus 16.
In the preceding description, the inputs of the multiplexers receive certain bits, but they could obviously also receive their complement. In this case it would merely be necessary to add to the represented circuit, a logic inverter between the code conversion circuit input and the multiplexer input. In the following examples, it is assumed that the inputs of the multiplexers receive the actual bits~
In practice ? each multiplexer is constituted by r elementary multiplexers having two inputs and an output. For example it is possible to use the multiplexer 74-LS 158 of Texas Instru-ments.
Two embodiments will now be described relative to Figs. 3 and 4.
The first embodiment corresponds to an alphanumeric display screen memory with 80x24 words using a 2048 word memory. With the pre-ceding notations, we have p=6 and q=4, as well as A=80 and B=24.
The relations defining r are then:
A' (2r l)x 26+1-r ~ 80 and B' 24 + 24-r ~ 24 The second inequation imposes 2 ~ 24-16, i.e. 24 r ~ 8, thus r=1. Consequently A'=64.
As A' does not exceed A, this solution is not suitable.
~L~
The test is repeated by permutating the two numbers A and B. Thus, on this occasion we take p=4 and q=6 with A=24 and B=80.
r is sought such that:
A~ = (2r-1) x 24+1 r ~ 24, and B' 26 + 26-r ~ 80 The second inequation gives 2 r 80-64=16 9 namely r=2. This means that A'=24, which is suitable. The solution is therefore p=4, q=6, r=2.
The multiplexing diagram is as follows and the multiplexed wires are again marked by an arrow:
M10 M9 M8 M7 M~ M5 M4 M3 M2 Ml M0 15 Y6=0: Y5 Y4 Y3 Y2 Y1 Y0 X4 X3 X2 Xl X0 Y6=1: X4 X3 Y3 Y2 Y1 Y0 "1" "1" X2 Xl X0 Thus, a memory circuit with 24 x 80 words is obtained and is shown in Fig. 3. It comprises a first multiplexer M(X) constituted by two multiplexers 2 ~ 1, respectively M(X)1 and M(X)2 whereof the inputs receive X3 and X4 on the one hand and two logic signals on the other. It oomprises a second multiplexer M(Y), which is also constituted by two multiplexers 2 ~ 1, respectively M(Y)1 and M(Y)2, whose inputs receive Y4, Y5 on the one hand and X3, X4 on the other. The most significant bit Y6 controls both of them. The memory MEM has 11 addressing inputs M0 to M10. The code conversion circuit CTA has five inputs for address X, namely X0 to X4, six inputs for address Y, namely Y0 to Y5 6~
plus the control inputs Y6 and ele~ren outputs S(X)O to S(X)4 and S(Y)O to S(Y)5.
The second embodiment corresponds to a graphic display screen memory with 27x2288 words using a 64k word memory. In this embodiment, we have p=4 and q=11 as well as A=27 and B=2288.
r is sought such that:
A' = (2 -1) X 2 1 r 27, and B' = 211 + 211-r 2288 The second inequation gives r=3, hence A' = 28, this solution being suitable. Thus, the following multiplexing diagram is obtained:
M~5 M14 M13 MU2 Mll M~0 M9 M8 M7 M6 M5 M4 M3 M2 Ml MD
if Yll=0 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Yl Y0 X4 X3 X2 Xl X0 if Yll=l X4 X3 X2 Y7 Y6 Y5 Y4 Y3 Y2 Yl Y0 "1" "1" "1" Xl X0 In this way, we obtain a memory with 28x2304 words, namely 1792x2304 points. Each word can consist of 64 bits in the case of the graphic display application. Fig. 4 shows the circuit obtained.
The address code conversion circuit has five inputs allocated to X (XO to X4) and twelve inputs allocated to Y (YO to Y11). The multi-plexers M(X) and M(Y) each comprise three multiplexers 2 ~ 1. The first multiplexer elements X2, X3, X4 with the same logic level "l' and the second multiplexer elements Y8, Y9, Y10 with X2, X3, X4. The multiplexing control is provided by Y11.
Claims (5)
1. A store for storing AxB words, in which A and B are numbers proving the inequations:
2p < A < 2p+1 2q < B < 2q+1 2p+q < AxB < 2p+q+1 in which p and q are integers, wherein it comprises p+q+1 addressing inputs connected to an address code conversion circuit (CTA) which is in two parts:
a) a first part (CTA)X constituted by:
- p+1 inputs E(X)O...E(X)p and p+1 outputs S(X)O...S(X)p, the p+1 inputs receiving p+1 bits (XO... Xp) defining a number X
lower than A, said bits being distributed between a least significant bit XO and a most significant bit Xp, the p+1 outputs being connected to p+1 first addressing inputs (MO...Mp) of the store MEM, - p+1-r direct connections CD(X) between the p+1-r inputs allocated to the p+1-r least significant bits of X and p+1-r outputs;
- a first multiplexer M(X) having a first group E(X)1 of the r inputs receiving logic expressions of the r most significant bits (Xp-r+1...Xp) of X received by the r corresponding inputs, and a second group e(X)2 of r inputs raised to the same pre-determined logic level, said first multiplex-er having r outputs s(X) connected to the r remaining outputs of said first part;
b. a second part CTA(Y) constituted by:
- q+1 inputs E(Y)O...E(Y)q and q outputs S(Y)O...S(Y)q-1, the q+1 inputs receiving the q+1 bits (YO...Yq) defining a number Y less than B, said bits being distributed between a least significant bit YO and a most significant bit Yq, the q outputs being connected to the q final addressing inputs (Mp+1...Mp+q) of the memory;
- q-r direct connections CD(Y) between the q-r inputs allocated to the q-r least significant bits Y and q-r outputs;
- a second multiplexer M(Y) having a first group e(Y)1 of r inputs receiving logic expressions of the r most significant bits (Yq-r+1...Yq-1) of Y taken after the most significant bit of Y (Yq) and a second group e(Y)2 of r inputs connected to the first group of r inputs e(X)1 of the first multi-plexer M(X) of the first part, said second multiplexer having r outputs s(Y) connected to the r remaining outputs s(X)q-r...S(Y)q-1 of said second part;
each multiplexer also having a control input C(X), C(Y), which receives the most significant bit Yq of the number Y applied to the most significant input E(Y)q of the second part, the r addressing inputs (Mp-r+1...Mp) of the store connected to the outputs of the first multiplexer M(X) thus receiving, according to the value of the most significant bit Yq of Y, either r logic expressions of the r most significant bits (Xp-r+1...Xp) of X, or r predetermined logic levels, and the r addressing inputs (Np+q-r+1...
Mp+q) of the store connected to the outputs Or the second multiplexer M(Y), receiving in the same way either the r most significant bits of Y taken after the most significant bit (Yq=r+1...Yq-1), or the r most significant bits of X (Xp-r+1...Xp), whereby hereinbefore r is an integer proving the relations:
(2r-1) 2p+1-r ? A
2q + 2q-r ? B
2p < A < 2p+1 2q < B < 2q+1 2p+q < AxB < 2p+q+1 in which p and q are integers, wherein it comprises p+q+1 addressing inputs connected to an address code conversion circuit (CTA) which is in two parts:
a) a first part (CTA)X constituted by:
- p+1 inputs E(X)O...E(X)p and p+1 outputs S(X)O...S(X)p, the p+1 inputs receiving p+1 bits (XO... Xp) defining a number X
lower than A, said bits being distributed between a least significant bit XO and a most significant bit Xp, the p+1 outputs being connected to p+1 first addressing inputs (MO...Mp) of the store MEM, - p+1-r direct connections CD(X) between the p+1-r inputs allocated to the p+1-r least significant bits of X and p+1-r outputs;
- a first multiplexer M(X) having a first group E(X)1 of the r inputs receiving logic expressions of the r most significant bits (Xp-r+1...Xp) of X received by the r corresponding inputs, and a second group e(X)2 of r inputs raised to the same pre-determined logic level, said first multiplex-er having r outputs s(X) connected to the r remaining outputs of said first part;
b. a second part CTA(Y) constituted by:
- q+1 inputs E(Y)O...E(Y)q and q outputs S(Y)O...S(Y)q-1, the q+1 inputs receiving the q+1 bits (YO...Yq) defining a number Y less than B, said bits being distributed between a least significant bit YO and a most significant bit Yq, the q outputs being connected to the q final addressing inputs (Mp+1...Mp+q) of the memory;
- q-r direct connections CD(Y) between the q-r inputs allocated to the q-r least significant bits Y and q-r outputs;
- a second multiplexer M(Y) having a first group e(Y)1 of r inputs receiving logic expressions of the r most significant bits (Yq-r+1...Yq-1) of Y taken after the most significant bit of Y (Yq) and a second group e(Y)2 of r inputs connected to the first group of r inputs e(X)1 of the first multi-plexer M(X) of the first part, said second multiplexer having r outputs s(Y) connected to the r remaining outputs s(X)q-r...S(Y)q-1 of said second part;
each multiplexer also having a control input C(X), C(Y), which receives the most significant bit Yq of the number Y applied to the most significant input E(Y)q of the second part, the r addressing inputs (Mp-r+1...Mp) of the store connected to the outputs of the first multiplexer M(X) thus receiving, according to the value of the most significant bit Yq of Y, either r logic expressions of the r most significant bits (Xp-r+1...Xp) of X, or r predetermined logic levels, and the r addressing inputs (Np+q-r+1...
Mp+q) of the store connected to the outputs Or the second multiplexer M(Y), receiving in the same way either the r most significant bits of Y taken after the most significant bit (Yq=r+1...Yq-1), or the r most significant bits of X (Xp-r+1...Xp), whereby hereinbefore r is an integer proving the relations:
(2r-1) 2p+1-r ? A
2q + 2q-r ? B
2. A store according to claim 1, wherein each multiplexer M(X), M(Y) is constituted by r multiplexers 2 ? 1.
3. A store according to claim 1, wherein the logic expressions of the bits are the bits them-selves.
4. A store according to claim 1, wherein it is able to process 24x80 words and wherein it com-prises a memory with 11 addressing inputs, and a code conversion circuit incorporating a first part having five inputs, five outputs and two multi-plexers 2 ? 1, as well as a second part with six addressing inputs, one control input and six outputs, as well as two multiplexers 2 ? 1.
5. A memory according to claim 15 wherein it is able to process 27x2288 words and comprises a store having 16 addressing inputs and an address code conversion circuit incorporating a first part with five inputs, five outputs and three multiplexers 2 ? 1, and a second part having eleven addressing inputs, a further control input, eleven outputs and three multiplexers 2 ? 1.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8301544 | 1983-02-01 | ||
| FR8301544A FR2540277A1 (en) | 1983-02-01 | 1983-02-01 | WORDS MEMORY PROVIDED WITH AN ADDRESS TRANSCODING CIRCUIT |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1216954A true CA1216954A (en) | 1987-01-20 |
Family
ID=9285493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000446408A Expired CA1216954A (en) | 1983-02-01 | 1984-01-31 | Word store equipped with an address code conversion circuit |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4586024A (en) |
| EP (1) | EP0120721B1 (en) |
| JP (1) | JPS59146492A (en) |
| CA (1) | CA1216954A (en) |
| DE (1) | DE3463702D1 (en) |
| FR (1) | FR2540277A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0795398B2 (en) * | 1986-05-27 | 1995-10-11 | 日本電気株式会社 | 1-chip microcomputer |
| JPH0823996B2 (en) * | 1986-08-11 | 1996-03-06 | エヌ・ベー・フィリップス・フルーイランペンファブリケン | Aggregation of two or more integrated semiconductor circuits |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5295932A (en) * | 1976-02-09 | 1977-08-12 | Hitachi Ltd | Memory device |
| JPS54146534A (en) * | 1978-05-09 | 1979-11-15 | Mitsubishi Electric Corp | Address conversion system |
| US4231021A (en) * | 1978-11-01 | 1980-10-28 | Gte Products Corporation | Address data converter |
-
1983
- 1983-02-01 FR FR8301544A patent/FR2540277A1/en active Granted
-
1984
- 1984-01-25 EP EP84400165A patent/EP0120721B1/en not_active Expired
- 1984-01-25 DE DE8484400165T patent/DE3463702D1/en not_active Expired
- 1984-01-30 US US06/574,903 patent/US4586024A/en not_active Expired - Lifetime
- 1984-01-31 CA CA000446408A patent/CA1216954A/en not_active Expired
- 1984-02-01 JP JP59016928A patent/JPS59146492A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP0120721B1 (en) | 1987-05-13 |
| FR2540277B1 (en) | 1985-03-22 |
| US4586024A (en) | 1986-04-29 |
| JPS59146492A (en) | 1984-08-22 |
| EP0120721A1 (en) | 1984-10-03 |
| FR2540277A1 (en) | 1984-08-03 |
| DE3463702D1 (en) | 1987-06-19 |
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