CA1209281A - Multi-level aluminum metallization structure for semiconductor device - Google Patents
Multi-level aluminum metallization structure for semiconductor deviceInfo
- Publication number
- CA1209281A CA1209281A CA000446407A CA446407A CA1209281A CA 1209281 A CA1209281 A CA 1209281A CA 000446407 A CA000446407 A CA 000446407A CA 446407 A CA446407 A CA 446407A CA 1209281 A CA1209281 A CA 1209281A
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- Prior art keywords
- layer
- silicon
- aluminum
- level
- metallization layer
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
MULTI-LEVEL ALUMINUM METALLIZATION STRUCTURE
FOR SEMICONDUCTOR DEVICE
Abstract of the Disclosure A semiconductor device having a multi-level metallization structure wherein the first level is of aluminum containing silicon, and the second level is either aluminum or aluminum containing silicon in an amount less than that contained in the first level. The two levels, where they contact each other, are sintered together, with some of the silicon from the first level being diffused into the second level so that the second level has a region, adjacent the junction between the two levels, which has a higher content of silicon than the remaining portion of the second level. When making the device, the surface of the first level, where it is to be joined with the second level, is etched to remove some of the aluminum, but not the silicon, which roughens this surface. The second level is applied on this roughened surface, and the device is heated to sinter the two levels together and diffuse the silicon into the second level.
FOR SEMICONDUCTOR DEVICE
Abstract of the Disclosure A semiconductor device having a multi-level metallization structure wherein the first level is of aluminum containing silicon, and the second level is either aluminum or aluminum containing silicon in an amount less than that contained in the first level. The two levels, where they contact each other, are sintered together, with some of the silicon from the first level being diffused into the second level so that the second level has a region, adjacent the junction between the two levels, which has a higher content of silicon than the remaining portion of the second level. When making the device, the surface of the first level, where it is to be joined with the second level, is etched to remove some of the aluminum, but not the silicon, which roughens this surface. The second level is applied on this roughened surface, and the device is heated to sinter the two levels together and diffuse the silicon into the second level.
Description
~z~
RCA 77,119 MULTI-LEVEL ALUMINUM METALLIZATION STRUCTURE
FOR SEMICONDUCTOR DEVICE
Back~round of the Invention 1 Field of the Invention The present invention pertains to a multi-level metallization structure for a semiconductor device, particularly an integrated circuit, and a method of making the same. More particularly, the present invention relates to a multi-level metallization structure which uses aluminum and which provides good ohmic contact between the levels.
RCA 77,119 MULTI-LEVEL ALUMINUM METALLIZATION STRUCTURE
FOR SEMICONDUCTOR DEVICE
Back~round of the Invention 1 Field of the Invention The present invention pertains to a multi-level metallization structure for a semiconductor device, particularly an integrated circuit, and a method of making the same. More particularly, the present invention relates to a multi-level metallization structure which uses aluminum and which provides good ohmic contact between the levels.
2. Description of the Prior Art In the manufacture of semiconductor integrated circuits, the trend is directed toward increasing the number of components per unit area of -the circuit chip in order to reduce the cost per circuit function. This increase is achieved by reducing the size of the components themselv~s and/or reducing the spacing between the components. However, one of the factors which limits the decrease in size and spacing is the area required by the metal interconnections used to connect the various components in a desired circuit.
one technique for overcoming the metal interconnection problem is to use multi-level metallization systems. Multi-level metalli~ation systems include forming contact openings through the particular insulating layer, which is over the substrate of the device, to some of the components in the substrate. A first metal layer is deposited on the insulating layer and in the contact openings. The first metal la~er is defined to form a portion of the overall metal interconnection system. A
second layer of insulating material is applied over the defined first metal layer, and openings are formed through the second insulating layer. Some of the openings can go completely through the insulating layers to some of the components in the substrate, and some of the openings merely go through the second insulating layer ~i~
8~
-2- RCA 77,119 to the defined first metal layer. A second metal layer is deposited on the second insulating layer and in the contact openings, and is defined to form the remaining portion of the overall interconnection system. Thus, the defined second metal layer is connected to some of the components in the substrate and to the defined first metal layer. Additional metal layers may be used if the circui-t is sufficiently complex to require them.
A metal commonly used for the metallization in an integrated circuit, because of its high conductivity, ease of application and relatively low cost, is aluminum or aluminum containing a small amount of silicon.
However, a problem with aluminum is that as soon as it is deposited and exposed to air, a thin layer of aluminum oxide is formed on the surface of the aluminum. Although this aluminum oxide is not a major problem when using aluminum as a single level of metallization, it is a problem for multi-level metallization. The oxide layer provides an insulating layer between the two metallization layers which creates a high resistance where the two layers contact each other. An attempt to minimize the high contact resistance by increasing the contact area has been made by making the area of the openings in the insulating layer between the metallization layers larger than the line width of the defined metallization layer.
~eating the device to about 400C to break up the aluminum oxide and sinter the two layrs together further reduces the resistance. However, it has been found that this does not completely remove the oxide so that the contact resistance is still higher than if no oxide is present.
Furthermore, overetching the dielectric to form the oversize contact opening causes undercutting of the dielectric. Undercut edges cause poor step coverage in subsequently deposited layers.
Summary of the Invention A semiconductor device includes a substrate of semiconductor material having a first layer of insulating material on a surface thereof and a first conductive layer
one technique for overcoming the metal interconnection problem is to use multi-level metallization systems. Multi-level metalli~ation systems include forming contact openings through the particular insulating layer, which is over the substrate of the device, to some of the components in the substrate. A first metal layer is deposited on the insulating layer and in the contact openings. The first metal la~er is defined to form a portion of the overall metal interconnection system. A
second layer of insulating material is applied over the defined first metal layer, and openings are formed through the second insulating layer. Some of the openings can go completely through the insulating layers to some of the components in the substrate, and some of the openings merely go through the second insulating layer ~i~
8~
-2- RCA 77,119 to the defined first metal layer. A second metal layer is deposited on the second insulating layer and in the contact openings, and is defined to form the remaining portion of the overall interconnection system. Thus, the defined second metal layer is connected to some of the components in the substrate and to the defined first metal layer. Additional metal layers may be used if the circui-t is sufficiently complex to require them.
A metal commonly used for the metallization in an integrated circuit, because of its high conductivity, ease of application and relatively low cost, is aluminum or aluminum containing a small amount of silicon.
However, a problem with aluminum is that as soon as it is deposited and exposed to air, a thin layer of aluminum oxide is formed on the surface of the aluminum. Although this aluminum oxide is not a major problem when using aluminum as a single level of metallization, it is a problem for multi-level metallization. The oxide layer provides an insulating layer between the two metallization layers which creates a high resistance where the two layers contact each other. An attempt to minimize the high contact resistance by increasing the contact area has been made by making the area of the openings in the insulating layer between the metallization layers larger than the line width of the defined metallization layer.
~eating the device to about 400C to break up the aluminum oxide and sinter the two layrs together further reduces the resistance. However, it has been found that this does not completely remove the oxide so that the contact resistance is still higher than if no oxide is present.
Furthermore, overetching the dielectric to form the oversize contact opening causes undercutting of the dielectric. Undercut edges cause poor step coverage in subsequently deposited layers.
Summary of the Invention A semiconductor device includes a substrate of semiconductor material having a first layer of insulating material on a surface thereof and a first conductive layer
-3- RCA 77,119 on the first insulating layer. A second layer of an insulating material is on the first conductive layer and has an opening therethrough to the ~irst conductive layer.
A second conductive layer is on the second insulating layer and extends through the opening therein and contacts the first conductive layer. The first conductive layer is of aluminum containing silicon and the second conductive layer is either aluminum or aluminum containing silicon in an amount less than that contained in the first conductive layer. In making the semiconductor device, the first conductive layer is applied over the first insulating layer, and the second insulating layer is applied over the first conductive layer. The openiny is ~ormed through the second insulating layer, and the exposed portion of the first conductive layer is etched with an etchant which removes the aluminum at the exposed surface but leaves exposed the precipitated silicon particles contained in the aluminum-silicon conductive layer. The second conductive layer is then applied, and the device is heated to anneal the second conductive layer to the first conductive layer at their interface in the opening in the second insulating layer.
Brief Description of the Drawin~
In the drawing:
FIGURE 1 is a cross-sectional view of a semiconductor device which incorporates the present invention.
FIGURES 2 through 5 are cross-sectional views illustrating the various steps of the method of the present invention for making the semiconductor device shown in FIGURE l.
Detailed Description of the Preferred Embodiment FI~URE l shows a semiconductor device, generally designated as 10, which includes the present invention.
The semiconductor device 10 includes a substrate 12 of a single-cyrstalline semiconductor material, such as silicon, having a major surface 14. Within the substrate 12 and along the surface 14 are various active and passive
A second conductive layer is on the second insulating layer and extends through the opening therein and contacts the first conductive layer. The first conductive layer is of aluminum containing silicon and the second conductive layer is either aluminum or aluminum containing silicon in an amount less than that contained in the first conductive layer. In making the semiconductor device, the first conductive layer is applied over the first insulating layer, and the second insulating layer is applied over the first conductive layer. The openiny is ~ormed through the second insulating layer, and the exposed portion of the first conductive layer is etched with an etchant which removes the aluminum at the exposed surface but leaves exposed the precipitated silicon particles contained in the aluminum-silicon conductive layer. The second conductive layer is then applied, and the device is heated to anneal the second conductive layer to the first conductive layer at their interface in the opening in the second insulating layer.
Brief Description of the Drawin~
In the drawing:
FIGURE 1 is a cross-sectional view of a semiconductor device which incorporates the present invention.
FIGURES 2 through 5 are cross-sectional views illustrating the various steps of the method of the present invention for making the semiconductor device shown in FIGURE l.
Detailed Description of the Preferred Embodiment FI~URE l shows a semiconductor device, generally designated as 10, which includes the present invention.
The semiconductor device 10 includes a substrate 12 of a single-cyrstalline semiconductor material, such as silicon, having a major surface 14. Within the substrate 12 and along the surface 14 are various active and passive
-4- RCA 77,119 devices, such as transistors, diodes and resistors, which are to be electrically connected in a deslred circuit arrangement. Illustrative of such devices are regions 16 and 18 which may be of different conductivity types from
5 that of the substrate 12 or of the same conductivity type but different resistivity. On the surface 14 of the substrate 12 is a first layer 20 of an insulating material, such as silicon dioxide. The first insulating layer 20 has a paix of openings 22 and ~4 therethrough to the regions 16 and 18, respectively. A first conductive layer 26 is on a portion of the first insulating layer 20 and extends into the opening 22 to contact the region 16.
The first conductive layer 26 is of aluminum containing silicon, preferably up to about 3 percent of silicon.
A second insulating layer 28 extends over the first conductive layer 26 and the portion of the first insulating layer 20 not covered by the first conductive layer 26. The second insulating layer 28 may be of an inorganic material, such as silicon dioxide or silicon nitride, or an organic material, such as a polyimid. The second insulating layer 28 has two openings 30 and 32 therethrough. The opening 30 extends to the first conductive layer 26, and the opening 32 is in alignment with the opening 24 in the first insulating layer 20 which extends to the region 18. A second conductive layer 34 is over a portion of the second insulating layer 28 and extends into the opening 30 to contact the first conductive layer 26 and through the aligned openings 32 and 24 to contact the region 18~ The second conductive layer 34 is either aluminum or aluminum containing silicon in an amount less than that contained in the first conductive layer 26. The conductive layers 26 and 34 are defined to form interconnecting strips to electrically ronnect the various devices in the substrate 12, such as the regions 16 and 18, together and to termination pads for the semiconductor device 10. As will be explained in detail hereinafter, the second conductive layer 34 has a sintered interface with the first conductive layer 26 and - ~ 2~4$~
~5- RCA 77,119 has a region adjacent the interface which contains an amount of silicon sreater than that which is contained in the remaining portion of the second conductive layer 34.
This provides a low-resistance contact between the two conductive layers 26 and 34.
To make the semiconductor device 10 using the method of the present invention, the regions 16 and 18 are formed in the substrate 12 using standard semiconductor technology, such as by ion implantation or diffusion. The first insulating layer 20 is then formed on the surface 14. If the first insulating layer 20 is of silicon dio~ide, it can ~e grown on the surface 14 by exposing the surface 14 to oxygen or steam at a temperature of between about 800C and 1200C. The opening 22 is then formed in the first insulating layer 20. This can be achieved by applying a layer of a photoresist over the entire surface of the first insulating layer 20 and patterning it where the opening 22 is to be formed using standard photolithographic techniques. The exposed portion of the first insulating layer 20 is then removed using a suitable etchant, such as buffered hydrofluoric acid for silicon dioxide.
The first conductive layer 26 is then formed.
This is achieved by coating a layer of the silicon-containing aluminum over the entire surface of the irsti~sulatin~ layer 20 and in the opening 22 using any standard deposition technique, such as evaporation in a vacuum or sputtering. A patterned layer of photoresist is formed over the portion of the silicon-containing aluminum which is to form the first conductive layer 26, using standard photolithographic techniques. The uncoated portion of the silicon-containins-aluminum layer is then removed using a suitable etching technique~ such as plasma etching or wet chemical etching with said solutions such as 20 parts H3PO4 to l part HN03 at about 50C. The photoresist layer is then removed.
As shown in FIGURE 3, the second insulating layer 28 is then coated over the first conductive layer 26 $~
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The first conductive layer 26 is of aluminum containing silicon, preferably up to about 3 percent of silicon.
A second insulating layer 28 extends over the first conductive layer 26 and the portion of the first insulating layer 20 not covered by the first conductive layer 26. The second insulating layer 28 may be of an inorganic material, such as silicon dioxide or silicon nitride, or an organic material, such as a polyimid. The second insulating layer 28 has two openings 30 and 32 therethrough. The opening 30 extends to the first conductive layer 26, and the opening 32 is in alignment with the opening 24 in the first insulating layer 20 which extends to the region 18. A second conductive layer 34 is over a portion of the second insulating layer 28 and extends into the opening 30 to contact the first conductive layer 26 and through the aligned openings 32 and 24 to contact the region 18~ The second conductive layer 34 is either aluminum or aluminum containing silicon in an amount less than that contained in the first conductive layer 26. The conductive layers 26 and 34 are defined to form interconnecting strips to electrically ronnect the various devices in the substrate 12, such as the regions 16 and 18, together and to termination pads for the semiconductor device 10. As will be explained in detail hereinafter, the second conductive layer 34 has a sintered interface with the first conductive layer 26 and - ~ 2~4$~
~5- RCA 77,119 has a region adjacent the interface which contains an amount of silicon sreater than that which is contained in the remaining portion of the second conductive layer 34.
This provides a low-resistance contact between the two conductive layers 26 and 34.
To make the semiconductor device 10 using the method of the present invention, the regions 16 and 18 are formed in the substrate 12 using standard semiconductor technology, such as by ion implantation or diffusion. The first insulating layer 20 is then formed on the surface 14. If the first insulating layer 20 is of silicon dio~ide, it can ~e grown on the surface 14 by exposing the surface 14 to oxygen or steam at a temperature of between about 800C and 1200C. The opening 22 is then formed in the first insulating layer 20. This can be achieved by applying a layer of a photoresist over the entire surface of the first insulating layer 20 and patterning it where the opening 22 is to be formed using standard photolithographic techniques. The exposed portion of the first insulating layer 20 is then removed using a suitable etchant, such as buffered hydrofluoric acid for silicon dioxide.
The first conductive layer 26 is then formed.
This is achieved by coating a layer of the silicon-containing aluminum over the entire surface of the irsti~sulatin~ layer 20 and in the opening 22 using any standard deposition technique, such as evaporation in a vacuum or sputtering. A patterned layer of photoresist is formed over the portion of the silicon-containing aluminum which is to form the first conductive layer 26, using standard photolithographic techniques. The uncoated portion of the silicon-containins-aluminum layer is then removed using a suitable etching technique~ such as plasma etching or wet chemical etching with said solutions such as 20 parts H3PO4 to l part HN03 at about 50C. The photoresist layer is then removed.
As shown in FIGURE 3, the second insulating layer 28 is then coated over the first conductive layer 26 $~
~,, .,~
-6- RCA 77,119 and the exposed portion of the first insulating layer 20.
If the second insulating layer is of an inorganic material, such as silicon dioxide or silicon nitride, it can be applied using a standard chemical vapor deposition technique wherein the device is exposed to a gas containing the elements of the second insulating layer and heated to react the gas to deposit the particular matexial. If the second insulating layer 28 is of an organic material, such as a polyimid, it can be painted or spun on and then cured. The openings 30 and 32 are then formed through the second insulating layer 28 by providing a layer of photoresist over the surface of the second i~sulating layer 28 and patterning it where the openings 30 and 32 are to be formed using standard photolithographic techniques. The exposed portions of the second insulating layer 28 are then removed using a suitable etching technique for the particular material used for the second insulating layer 28. The opening 24 in the first insulating layer 20 can then be formed by etching the surface of the first insulating layer 20 exposed at the bottom of the opening 32 in the second insulating layer 28. ~f the second insulating layer 28 is of the same material as the first insulating layer 24, when the opening 32 is formed the etching technique will ~5 automatically also etch through the first insula-ting layer 20 to form the opaning ~4. However, if the second insulating layer 24 is of a material different from that of the fixst insulating layer 20, after the opening 32 is formed an appropriate etching technique is then used to form the opening 24.
The surface of the first conductive layer 26 exposed at the bottom of the opening 30 in the second insulating layer 28 is then subjected to an etchant which will etch aluminum, but does not etch siliconO As shown in FIGURE 4, this will etch away a portion of the aluminum at thP exposed surface, leaving silicon particles 36 projecting from the exposed surface. Preferably, about 1000 Angstroms of the aluminum are removed from the
If the second insulating layer is of an inorganic material, such as silicon dioxide or silicon nitride, it can be applied using a standard chemical vapor deposition technique wherein the device is exposed to a gas containing the elements of the second insulating layer and heated to react the gas to deposit the particular matexial. If the second insulating layer 28 is of an organic material, such as a polyimid, it can be painted or spun on and then cured. The openings 30 and 32 are then formed through the second insulating layer 28 by providing a layer of photoresist over the surface of the second i~sulating layer 28 and patterning it where the openings 30 and 32 are to be formed using standard photolithographic techniques. The exposed portions of the second insulating layer 28 are then removed using a suitable etching technique for the particular material used for the second insulating layer 28. The opening 24 in the first insulating layer 20 can then be formed by etching the surface of the first insulating layer 20 exposed at the bottom of the opening 32 in the second insulating layer 28. ~f the second insulating layer 28 is of the same material as the first insulating layer 24, when the opening 32 is formed the etching technique will ~5 automatically also etch through the first insula-ting layer 20 to form the opaning ~4. However, if the second insulating layer 24 is of a material different from that of the fixst insulating layer 20, after the opening 32 is formed an appropriate etching technique is then used to form the opening 24.
The surface of the first conductive layer 26 exposed at the bottom of the opening 30 in the second insulating layer 28 is then subjected to an etchant which will etch aluminum, but does not etch siliconO As shown in FIGURE 4, this will etch away a portion of the aluminum at thP exposed surface, leaving silicon particles 36 projecting from the exposed surface. Preferably, about 1000 Angstroms of the aluminum are removed from the
-7- RCA 77,119 exposed surface to achieve a roughened surface provided by the projecting silicon particles 36. Etchants which have been found suitable for this purpose include mixtures of H3PO4 and HNO3, buffered hydrofluoric acid, dilute -hydrofluoric acid, and solutions of H20, HF, and CuS0~.The mixture containing CUS04 has been found to work extremely well since copper is plated onto the silicon particles as they are exposed and, depending on the size and density of the silicon particles, limits the etching of the aluminum. The copper-plat~d surface is then immersed in HN03 to remove the copper and to P~pose a surface having a high density of silicon particles. This etching step removes any aluminum oxide from the exposed surface and also provides a roughened surface.
The second conductive layer 34 is then formed by depositing a layer of aluminum or aluminum containing an amount of silicon less than that contained in the first ~onductive layer 26, over the entire surface of the second insulating layer 28 and in the openings 30, 32 and 24.
The metal layer is then defined to form the second sonductive layer 34 by applying a photoresist over the metal layer and pattexning the photoresist so that it covers only the portion of the metal layer which is to form the second conductive layer 34. The uncovered portion of the metal layer is t~en removed using a suitable etching techni~ue.
The device 10 is then heated at a temperature of about 400C to sinter the second conductive layer 34 to the first conductive layer 26. During sintering, the silicon particles 36 of the ~irst conductive layer 26 are dissolved in the second conductive layer, and additional silicon will diffuse from the first conductive layer 26 into the second conductive layer 34 which contains less silicon than that contained in the first conductive layer 26. Aluminum-silicon will fill areas where the silicon had previously been located at the interface between the two conductive layers. As sho~n in FIGURE 5, this provides a region 34a in the second conductive layer 34,
The second conductive layer 34 is then formed by depositing a layer of aluminum or aluminum containing an amount of silicon less than that contained in the first ~onductive layer 26, over the entire surface of the second insulating layer 28 and in the openings 30, 32 and 24.
The metal layer is then defined to form the second sonductive layer 34 by applying a photoresist over the metal layer and pattexning the photoresist so that it covers only the portion of the metal layer which is to form the second conductive layer 34. The uncovered portion of the metal layer is t~en removed using a suitable etching techni~ue.
The device 10 is then heated at a temperature of about 400C to sinter the second conductive layer 34 to the first conductive layer 26. During sintering, the silicon particles 36 of the ~irst conductive layer 26 are dissolved in the second conductive layer, and additional silicon will diffuse from the first conductive layer 26 into the second conductive layer 34 which contains less silicon than that contained in the first conductive layer 26. Aluminum-silicon will fill areas where the silicon had previously been located at the interface between the two conductive layers. As sho~n in FIGURE 5, this provides a region 34a in the second conductive layer 34,
-8- RCA 77,119 at the interface between the second conductive layer 34 and the first conductive layer 26, which has a content of silicon greater than that contained in the remaining portion of the second conductive layer 34. This sintering of the two conductive layers 26 and 34 provides a good electrical contact between the two layers. Furthermore, the diffusion of the silicon through the interface also breaks up any oxide that was formed on the exposed aluminum, and since the top surface of the first conductive layer 26 contains a high density of silicon particles, the area of aluminum exposed to oxidation is reduced considerably. All of these factors serve to provide a good low-resistance contact, and this low-resistance contact can be achieved with very small area contact regions.
The following Examples are given to further illustrate the present invention and are not to be taken in any way as restricting the invention beyond the scope of the appended claims.
EXAMPLE I
A group of test pattern devices were made with each device being made by first growing a layer of silicon dioxide on a surface of a single-crystalline-silicon substrate by heating the substrate in steam at a temperature of about 1100C. A first metal layer was coated on the silicon dioxide layer by sputtering. The first metal la~er was then defined to form forty-five (45) islands of the metal, each island being 32 micrometers by 70 micrometers in size. A layer of silica glass containing 3 percent by weight of phosphorous was deposited over the substrate and the first metal island by a chemical vapor deposition process at atmospheric pressure. Ninety (90) openings, each measuring about 10 micromekers by 10 micrometers, were etched through the phosphorous-silica glass to the first metal island using buffered hydrofluoric acid. The openings were arranged so that there were two openings to each metal island, with the openings being uniformly spaced across the islands as ~Z~$~
~9- RCA 77,119 well as un.iformly spaced rom island to island. The etching of the openings was carried out long enough to etch the surface of the first metal islands at the bottom of each opening. A second metal layer was then deposited by sputtering ovex the glass layer and in the openings to contact the first islands. The second metal layer was defined to form ~ plurality of islands, each 32 micrometers by 70 micrometers in size, with each island extending from an openin~ to one of the first islands to an opening to an adjacent first island. Thus, the second islands electrically connected the first islands in series, which included the contacts between the second islands and the first islands. The devices were then heated at 450C for 4 hours to anneal the second islands to the first islands.
All of the devices made used aluminum as the second metal layer to form the second islands. In some of the devices, the second metal layer of aluminum was one micrometer in thickness, and in other devices the second metal layex of aluminum was two micrometers in thickness.
In some of the devices, the first metal layer was aluminum. In other devices, the first metal layer was aluminum containing 1 percent of silicon, and in some of the devices the first metal layer was aluminum containing 2 percent of silicon.
For each device, the resistance of the series-con~ected islands was measured. The measured resistance was divided by 90, the number of contacts betw~en the first and second islands, to determine the average contact resistance at each interface between the first and second islands plus the resistance of the metal line between the contact points. Table 1 shows the average resistance for each of the devices.
-10- RCA 77,119 Metal Resistance (First layer/second layer) ~ohms) Al/Al Too high to measure Al-Si (1%)/Al(l~) . 177 Al-Si (1%)/Al(2~) . 136 Al Si (2%)/Al(l~) . 168 Al-Si (2%)/Al~2~) .0875 EXAMPLE II
A group of test pattern devices was made in the same mannex as described in Example I except that the openings through the phosphorous-silica glass were about 15 micrometers by 15 micrometers in size. Table 2 shows the average resistance for each of the devices.
Metal Resistance (First layer/second layer) (ohms) Al/Al .153 Al-Si (1%)/Al (1~) .113 Al-Si (1%)~Al (2~) .092 Al-Si (2%)/Al (1~) .1 Al-Si (2%)/A1 ~2~) .061 EXAMPLE III
A group of test pattern devices was made in the same manner as described in Example I except that the openings through the phosphorous silica glass were about 20 micrometers by 20 micrometers in size. Table 3 shows the average resistance for each of the devices.
'r;~t~
-11- RCA 77, 119 Metal Resistance (First layer/second layer) ~ohms) Al/Al .128 Al-Si (1%)/Al (1~) .1 Al-Si (1%)/Al (2~) .073 A1-Si (2%)/Al (l~) .091 Al-Si (2%)/Al (2~) .053 From the above Tables, lt can be seen that those devices which used silicon-containing aluminum as the first metal had lower contact resistance than the devices in which both metal layers were aluminum. Also, the higher the silicon content of the first metal layer, the lower the contact resistance. In addition, the thicker the second aluminum layer the lower the contact resistance.
The following Examples are given to further illustrate the present invention and are not to be taken in any way as restricting the invention beyond the scope of the appended claims.
EXAMPLE I
A group of test pattern devices were made with each device being made by first growing a layer of silicon dioxide on a surface of a single-crystalline-silicon substrate by heating the substrate in steam at a temperature of about 1100C. A first metal layer was coated on the silicon dioxide layer by sputtering. The first metal la~er was then defined to form forty-five (45) islands of the metal, each island being 32 micrometers by 70 micrometers in size. A layer of silica glass containing 3 percent by weight of phosphorous was deposited over the substrate and the first metal island by a chemical vapor deposition process at atmospheric pressure. Ninety (90) openings, each measuring about 10 micromekers by 10 micrometers, were etched through the phosphorous-silica glass to the first metal island using buffered hydrofluoric acid. The openings were arranged so that there were two openings to each metal island, with the openings being uniformly spaced across the islands as ~Z~$~
~9- RCA 77,119 well as un.iformly spaced rom island to island. The etching of the openings was carried out long enough to etch the surface of the first metal islands at the bottom of each opening. A second metal layer was then deposited by sputtering ovex the glass layer and in the openings to contact the first islands. The second metal layer was defined to form ~ plurality of islands, each 32 micrometers by 70 micrometers in size, with each island extending from an openin~ to one of the first islands to an opening to an adjacent first island. Thus, the second islands electrically connected the first islands in series, which included the contacts between the second islands and the first islands. The devices were then heated at 450C for 4 hours to anneal the second islands to the first islands.
All of the devices made used aluminum as the second metal layer to form the second islands. In some of the devices, the second metal layer of aluminum was one micrometer in thickness, and in other devices the second metal layex of aluminum was two micrometers in thickness.
In some of the devices, the first metal layer was aluminum. In other devices, the first metal layer was aluminum containing 1 percent of silicon, and in some of the devices the first metal layer was aluminum containing 2 percent of silicon.
For each device, the resistance of the series-con~ected islands was measured. The measured resistance was divided by 90, the number of contacts betw~en the first and second islands, to determine the average contact resistance at each interface between the first and second islands plus the resistance of the metal line between the contact points. Table 1 shows the average resistance for each of the devices.
-10- RCA 77,119 Metal Resistance (First layer/second layer) ~ohms) Al/Al Too high to measure Al-Si (1%)/Al(l~) . 177 Al-Si (1%)/Al(2~) . 136 Al Si (2%)/Al(l~) . 168 Al-Si (2%)/Al~2~) .0875 EXAMPLE II
A group of test pattern devices was made in the same mannex as described in Example I except that the openings through the phosphorous-silica glass were about 15 micrometers by 15 micrometers in size. Table 2 shows the average resistance for each of the devices.
Metal Resistance (First layer/second layer) (ohms) Al/Al .153 Al-Si (1%)/Al (1~) .113 Al-Si (1%)~Al (2~) .092 Al-Si (2%)/Al (1~) .1 Al-Si (2%)/A1 ~2~) .061 EXAMPLE III
A group of test pattern devices was made in the same manner as described in Example I except that the openings through the phosphorous silica glass were about 20 micrometers by 20 micrometers in size. Table 3 shows the average resistance for each of the devices.
'r;~t~
-11- RCA 77, 119 Metal Resistance (First layer/second layer) ~ohms) Al/Al .128 Al-Si (1%)/Al (1~) .1 Al-Si (1%)/Al (2~) .073 A1-Si (2%)/Al (l~) .091 Al-Si (2%)/Al (2~) .053 From the above Tables, lt can be seen that those devices which used silicon-containing aluminum as the first metal had lower contact resistance than the devices in which both metal layers were aluminum. Also, the higher the silicon content of the first metal layer, the lower the contact resistance. In addition, the thicker the second aluminum layer the lower the contact resistance.
Claims (5)
1. A method of forming a multi-level metallization on a substrate comprising the steps of:
forming a first metallization layer of aluminum containing up to 3 percent of silicon over a surface of a substrate, forming a layer of an insulating material over the first metallization layer, forming an opening through the insulating layer to the first metallization layer, forming a second metallization layer of aluminum containing silicon in an amount less than that contained in the first metallization layer over the insulating layer and in the opening to contact the first metallization layer, and heating the metallization layers to sinter the two layers together at their junction within the opening in the insulating layer and to diffuse some of the silicon from the first metallization layer into the second metallization layer.
forming a first metallization layer of aluminum containing up to 3 percent of silicon over a surface of a substrate, forming a layer of an insulating material over the first metallization layer, forming an opening through the insulating layer to the first metallization layer, forming a second metallization layer of aluminum containing silicon in an amount less than that contained in the first metallization layer over the insulating layer and in the opening to contact the first metallization layer, and heating the metallization layers to sinter the two layers together at their junction within the opening in the insulating layer and to diffuse some of the silicon from the first metallization layer into the second metallization layer.
2. The method in accordance with claim 1 in which prior to forming the second metallization layer, the surface of the first metallization layer in the opening in the insulating layer is treated to remove some of the aluminum and expose some of the silicon particles at the surface of the first metallization layer.
3. The method in accordance with claim 2 in which the first metallization layer is treated by subjecting it to an etchant which removes aluminum, but not silicon.
4. A method of forming a multi-level metallization on a substrate comprising the steps of:
forming a first metallization layer of aluminum containing up to 3 percent of silicon over a surface of the substrate, forming a layer of an insulating material over the first metallization layer, forming an opening through the insulating layer to the first metallization layer, treating the surface of the first metallization layer in the opening in the insulating layer to remove some of the aluminum and expose some of the silicon particles at the surface of the first metallization layer, forming a second metallization layer of either aluminum or aluminum containing silicon in an amount less than that contained in the first metallization layer over the insulating layer and in the opening to contact the first metallization layer, and heating the metallization layers to sinter the two layers together at their junction within the opening in the insulating layer and to diffuse some of the silicon from the first metallization layer into the second metallization layer.
forming a first metallization layer of aluminum containing up to 3 percent of silicon over a surface of the substrate, forming a layer of an insulating material over the first metallization layer, forming an opening through the insulating layer to the first metallization layer, treating the surface of the first metallization layer in the opening in the insulating layer to remove some of the aluminum and expose some of the silicon particles at the surface of the first metallization layer, forming a second metallization layer of either aluminum or aluminum containing silicon in an amount less than that contained in the first metallization layer over the insulating layer and in the opening to contact the first metallization layer, and heating the metallization layers to sinter the two layers together at their junction within the opening in the insulating layer and to diffuse some of the silicon from the first metallization layer into the second metallization layer.
5. The method in accordance with claim 4 in which the first metallization layer is treated by subjecting it to an etchant which removes aluminum, but not silicon.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US46564083A | 1983-02-10 | 1983-02-10 | |
| US465,640 | 1983-02-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1209281A true CA1209281A (en) | 1986-08-05 |
Family
ID=23848579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000446407A Expired CA1209281A (en) | 1983-02-10 | 1984-01-31 | Multi-level aluminum metallization structure for semiconductor device |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPH0666313B2 (en) |
| KR (1) | KR910008104B1 (en) |
| CA (1) | CA1209281A (en) |
| GB (1) | GB2135123B (en) |
| IT (1) | IT1213136B (en) |
| SE (1) | SE501466C2 (en) |
| YU (1) | YU18284A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0763064B2 (en) * | 1986-03-31 | 1995-07-05 | 株式会社日立製作所 | Wiring connection method for IC element |
| JPH0719841B2 (en) * | 1987-10-02 | 1995-03-06 | 株式会社東芝 | Semiconductor device |
| USRE36475E (en) * | 1993-09-15 | 1999-12-28 | Hyundai Electronics Industries Co., Ltd. | Method of forming a via plug in a semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51112292A (en) * | 1975-03-28 | 1976-10-04 | Hitachi Ltd | Semiconductor device |
| JPS55156365A (en) * | 1979-05-24 | 1980-12-05 | Toshiba Corp | Semiconductor device |
-
1984
- 1984-01-26 GB GB08402109A patent/GB2135123B/en not_active Expired
- 1984-01-31 CA CA000446407A patent/CA1209281A/en not_active Expired
- 1984-02-02 YU YU00182/84A patent/YU18284A/en unknown
- 1984-02-06 SE SE8400592A patent/SE501466C2/en unknown
- 1984-02-09 JP JP59024197A patent/JPH0666313B2/en not_active Expired - Lifetime
- 1984-02-09 IT IT8419546A patent/IT1213136B/en active
- 1984-02-10 KR KR1019840000622A patent/KR910008104B1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| GB8402109D0 (en) | 1984-02-29 |
| IT1213136B (en) | 1989-12-14 |
| SE501466C2 (en) | 1995-02-20 |
| KR840008215A (en) | 1984-12-13 |
| JPH0666313B2 (en) | 1994-08-24 |
| GB2135123B (en) | 1987-05-20 |
| SE8400592L (en) | 1984-08-11 |
| KR910008104B1 (en) | 1991-10-07 |
| YU18284A (en) | 1987-12-31 |
| JPS59205739A (en) | 1984-11-21 |
| IT8419546A0 (en) | 1984-02-09 |
| GB2135123A (en) | 1984-08-22 |
| SE8400592D0 (en) | 1984-02-06 |
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