YU18284A - Process for forming multi-layered metallic structure for semiconductor device - Google Patents
Process for forming multi-layered metallic structure for semiconductor deviceInfo
- Publication number
- YU18284A YU18284A YU00182/84A YU18284A YU18284A YU 18284 A YU18284 A YU 18284A YU 00182/84 A YU00182/84 A YU 00182/84A YU 18284 A YU18284 A YU 18284A YU 18284 A YU18284 A YU 18284A
- Authority
- YU
- Yugoslavia
- Prior art keywords
- semiconductor device
- metallic structure
- forming multi
- layered metallic
- layered
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US46564083A | 1983-02-10 | 1983-02-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
YU18284A true YU18284A (en) | 1987-12-31 |
Family
ID=23848579
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
YU00182/84A YU18284A (en) | 1983-02-10 | 1984-02-02 | Process for forming multi-layered metallic structure for semiconductor device |
Country Status (7)
Country | Link |
---|---|
JP (1) | JPH0666313B2 (en) |
KR (1) | KR910008104B1 (en) |
CA (1) | CA1209281A (en) |
GB (1) | GB2135123B (en) |
IT (1) | IT1213136B (en) |
SE (1) | SE501466C2 (en) |
YU (1) | YU18284A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0763064B2 (en) * | 1986-03-31 | 1995-07-05 | 株式会社日立製作所 | Wiring connection method for IC element |
JPH0719841B2 (en) * | 1987-10-02 | 1995-03-06 | 株式会社東芝 | Semiconductor device |
USRE36475E (en) * | 1993-09-15 | 1999-12-28 | Hyundai Electronics Industries Co., Ltd. | Method of forming a via plug in a semiconductor device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51112292A (en) * | 1975-03-28 | 1976-10-04 | Hitachi Ltd | Semiconductor device |
JPS55156365A (en) * | 1979-05-24 | 1980-12-05 | Toshiba Corp | Semiconductor device |
-
1984
- 1984-01-26 GB GB08402109A patent/GB2135123B/en not_active Expired
- 1984-01-31 CA CA000446407A patent/CA1209281A/en not_active Expired
- 1984-02-02 YU YU00182/84A patent/YU18284A/en unknown
- 1984-02-06 SE SE8400592A patent/SE501466C2/en unknown
- 1984-02-09 JP JP59024197A patent/JPH0666313B2/en not_active Expired - Lifetime
- 1984-02-09 IT IT8419546A patent/IT1213136B/en active
- 1984-02-10 KR KR1019840000622A patent/KR910008104B1/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
GB8402109D0 (en) | 1984-02-29 |
IT1213136B (en) | 1989-12-14 |
SE501466C2 (en) | 1995-02-20 |
KR840008215A (en) | 1984-12-13 |
JPH0666313B2 (en) | 1994-08-24 |
GB2135123B (en) | 1987-05-20 |
CA1209281A (en) | 1986-08-05 |
SE8400592L (en) | 1984-08-11 |
KR910008104B1 (en) | 1991-10-07 |
JPS59205739A (en) | 1984-11-21 |
IT8419546A0 (en) | 1984-02-09 |
GB2135123A (en) | 1984-08-22 |
SE8400592D0 (en) | 1984-02-06 |
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