CA1193028A - Sto stack control system for multi-virtual memory in a data processing system - Google Patents

Sto stack control system for multi-virtual memory in a data processing system

Info

Publication number
CA1193028A
CA1193028A CA000412068A CA412068A CA1193028A CA 1193028 A CA1193028 A CA 1193028A CA 000412068 A CA000412068 A CA 000412068A CA 412068 A CA412068 A CA 412068A CA 1193028 A CA1193028 A CA 1193028A
Authority
CA
Canada
Prior art keywords
sto
stack
contents
control
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000412068A
Other languages
English (en)
French (fr)
Inventor
Masayuki Ohya
Masaaki Inou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of CA1193028A publication Critical patent/CA1193028A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Storage Device Security (AREA)
CA000412068A 1981-09-25 1982-09-23 Sto stack control system for multi-virtual memory in a data processing system Expired CA1193028A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP152514/81 1981-09-25
JP56152514A JPS5853079A (ja) 1981-09-25 1981-09-25 Ｓｔｏスタツク制御方式

Publications (1)

Publication Number Publication Date
CA1193028A true CA1193028A (en) 1985-09-03

Family

ID=15542106

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000412068A Expired CA1193028A (en) 1981-09-25 1982-09-23 Sto stack control system for multi-virtual memory in a data processing system

Country Status (9)

Country Link
US (1) US4490787A (enExample)
EP (1) EP0076097B1 (enExample)
JP (1) JPS5853079A (enExample)
KR (1) KR860002029B1 (enExample)
AU (1) AU534594B2 (enExample)
BR (1) BR8205606A (enExample)
CA (1) CA1193028A (enExample)
DE (1) DE3279574D1 (enExample)
ES (1) ES515938A0 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS593642A (ja) 1982-06-30 1984-01-10 Fujitsu Ltd 制御レジスタ処理方式
USRE37305E1 (en) * 1982-12-30 2001-07-31 International Business Machines Corporation Virtual memory address translation mechanism with controlled data persistence
JPS63195569U (enExample) * 1987-03-06 1988-12-15
US5023773A (en) * 1988-02-10 1991-06-11 International Business Machines Corporation Authorization for selective program access to data in multiple address spaces
US4945480A (en) * 1988-02-10 1990-07-31 International Business Machines Corporation Data domain switching on program address space switching and return
EP0464333A3 (en) * 1990-07-03 1992-07-29 International Business Machines Corporation Virtual memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3781808A (en) * 1972-10-17 1973-12-25 Ibm Virtual memory system
JPS51115737A (en) * 1975-03-24 1976-10-12 Hitachi Ltd Adress conversion versus control system
US4136385A (en) * 1977-03-24 1979-01-23 International Business Machines Corporation Synonym control means for multiple virtual storage systems
JPS54111726A (en) * 1978-02-22 1979-09-01 Hitachi Ltd Control unit for multiplex virtual memory
US4430705A (en) * 1980-05-23 1984-02-07 International Business Machines Corp. Authorization mechanism for establishing addressability to information in another address space

Also Published As

Publication number Publication date
EP0076097B1 (en) 1989-03-22
ES8306912A1 (es) 1983-06-01
KR840001732A (ko) 1984-05-16
BR8205606A (pt) 1983-08-30
AU8854082A (en) 1983-03-31
JPS5853079A (ja) 1983-03-29
EP0076097A3 (en) 1985-03-20
EP0076097A2 (en) 1983-04-06
JPS6214863B2 (enExample) 1987-04-04
ES515938A0 (es) 1983-06-01
KR860002029B1 (ko) 1986-11-15
US4490787A (en) 1984-12-25
DE3279574D1 (en) 1989-04-27
AU534594B2 (en) 1984-02-09

Similar Documents

Publication Publication Date Title
US4057848A (en) Address translation system
EP0851357B1 (en) Method and apparatus for preloading different default address translation attributes
US5101346A (en) Virtual machine system having a plurality of real instruction processors and virtual machines, and a registration table
US4068303A (en) Address translation managing system with translation pair purging
EP0098168B1 (en) Address translation buffer control system
EP0701211A2 (en) Data processor with address translation mechanism
SE7704968L (sv) Nyckelstyrt adressrelokeringsomvandlingssystem
JPS63231550A (ja) 多重仮想空間制御方式
US5437016A (en) Apparatus and method for translating logical addresses for virtual machines
US4961135A (en) Translation lookaside buffer control system
JP3454854B2 (ja) メモリ管理装置及び方法
US4490787A (en) STO Stack control system
JPS61156347A (ja) 仮想アドレス及びアクシヨンワードを並列にチエツクするメモリアクセス制御装置
JPS63298485A (ja) 画像処理装置
JP3190700B2 (ja) アドレス変換装置
US4424564A (en) Data processing system providing dual storage of reference bits
JPS5953634B2 (ja) 計算機システム
JP2659007B2 (ja) 情報処理方法及び装置
JPS6024491B2 (ja) アドレス変換制御方式
JP3015528B2 (ja) アドレス変換バッファ機構
EP0224168A2 (en) Buffer storage control system
JPS5838877B2 (ja) デ−タ処理装置
JPH06139146A (ja) キャッシュメモリ
JPS6143744B2 (enExample)
JPH02176839A (ja) 情報処理装置

Legal Events

Date Code Title Description
MKEC Expiry (correction)
MKEX Expiry
MKEX Expiry

Effective date: 20020923