CA1151257A - Edge termination for an electrical circuit device - Google Patents

Edge termination for an electrical circuit device

Info

Publication number
CA1151257A
CA1151257A CA000378327A CA378327A CA1151257A CA 1151257 A CA1151257 A CA 1151257A CA 000378327 A CA000378327 A CA 000378327A CA 378327 A CA378327 A CA 378327A CA 1151257 A CA1151257 A CA 1151257A
Authority
CA
Canada
Prior art keywords
termination
electrical circuit
planar surface
edge
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000378327A
Other languages
French (fr)
Inventor
John E. Bartley
Orville R. Penrod
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Allen Bradley Co LLC
Original Assignee
Allen Bradley Co LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Allen Bradley Co LLC filed Critical Allen Bradley Co LLC
Application granted granted Critical
Publication of CA1151257A publication Critical patent/CA1151257A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165Containers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3405Edge mounted components, e.g. terminals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0272Adaptations for fluid transport, e.g. channels, holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09145Edge details
    • H05K2201/09163Slotted edge
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09145Edge details
    • H05K2201/09181Notches in edge pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/1034Edge terminals, i.e. separate pieces of metal attached to the edge of the printed circuit board [PCB]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Details Of Resistors (AREA)

Abstract

EDGE TERMINATION FOR AN ELECTRICAL CIRCUIT DEVICE

Abstract of the Disclosure An electrical circuit device having a ceramic substrate including a thick or thin film circuit on at least one surface thereof and an intersecting edge surface which may support termination leads anchored thereto and further retained by solder deposited upon an edge termination coating. The termination coating underlying the solder extends over the edge defined by the intersecting surfaces. The component resides in form of the substrate to include an indented area in the form of a notch or a groove which intersects both adjoin-ing surfaces to provide a means of receiving edge termination material, so as to insure a continuous and non-interrupted deposit of the material to complete the electrical circuit between the leads and the respective circuit components of the circuit defined on the said one substrate surface.

Description

;Z57 EDGE TE~ ATlON FOR A~- ELECTRICAL CIRCUIT DEVICE

B k~round of the Inventio ~ he invention relates to electrical circuit de~-ices, and particularly to a method and means for electrically connecting S terminal leads, which extend outwardly from one surface of an insulating substrate, to electrical circuitry deposited on an adjoining surface of the substrate.
Over the past few years, there has been increased activity in providing electrical circuit components as printed or otherwise deposited configurations disposed on one or more surfaces of an insulating substrate member. The material of the substrate member is usually steatite, alumina or other ceramic based composition. Although the deposition of the materials required for supporting the elec'rical circuitry ls usually quite sufficient with regard to the particular adjoining sur-faces involved, very often it is difficult to insure that there will be an adequate thickness of the deposition of con-ducting edge termination material at the intersecting edse o the two adjacent surfaces. The conductin~ edge termi~ation material is arranged to complete the circuit between ~e-mination leads extending outwardly from one edge and the adjacent intar-secting surface which is intended to support the thick or thin film circuitry deposited thereon. The edge termina~ion material underlies the deposited circuit layer(s) and under a solder layer on an adjoining surface in supporting contact with ter-minal leads projecting outwardly from that surface. The cir-cuitry may be relatively simple, as fo instance, a ~esistor network, capaci_o. electrod~s or may inc'ude relatively cGmple~
semiconductor portions in ':he form of attached chip~ or othe_ devices which ccm~rise a h~brid assem~ly.

~' Devices, such as those to be hereinafter described, are made in relatively large quantities and are preferably arranged for automated manufacture. That is, the leads are very often attached by using conventional lead frame preforms, or other support carriers for a multiplicity of leads, and are further anchored to the substrate by means of solder applied with well-known solder flow bath or similar facilities. Thus, the leads may be initially held in place by wedging into a substrate opening and transported through a solder flow bath, where the solder will cling to the inner ends of the leads and to deposited solder-accepting edge termination areas applied to a surface of the substrate. The solder does not adhere to other portions of the substrate or the circuit. Techniques of this nature are dis-closed in the electrical circuit devices illustrated and claimed 15 in the Bartley et al U.S. Patent Nos. 4,127,934; 4,187,529 and 4,213,113, and the Beckman et al U.S. Patent No. 3,873,890, all patents being assigned to the same assignee as the present inven-tion. The first mentioned patent relates to a single in-line packaging technique, (SIP), whereas the Beckman et al patent is directed to a dual in-line package (DIP).
Inasmuch as the edge termination composition is con-ventionally made from a material, such as silver, which tends to go into solution with a later-deposited solder layer, there is always present the possibility of leaching away of termination ; 25 material which has been deposited on the adjoining surfaces dur-ing soldering operations. This deposition is usually applied by a transfer roller and often is thinnest at the relatively sharp edge defining the intersectiGn of the two angularly rela-tive surfaces. The Applicants are aware of some manufacturers who even go so far as to hand paint this sharp edge to insure a greater thickness of termination material. Obviously, this is a very expensive operation.

llS12S7 The applicants in researching this problem conceived of the present invention, which resides principally in provid;ng an indentation extending between the adjoining surfaces and traversing the aforementioned relatively sharp lines of intersection. This indentation may take the form of a simple notch at the line of intersection, or is preferably provided by means of a groove extending across the edge or surface which supports the terminal leads of conventional parallelepiped-formed dual in-line or single in-line packaged components, The groove finds its preference in the fact that molding dies used to press the ceramic substrate to form are easier to machine with a groove, as opposed to 6eing machined to provide a plurality of relatively small protrusions arranged to form notched areas in the substrate. These projections used for notching are also relatively small and subject to early abrasive wear during use of the dies.
Summaryofthe Invent;on This invention relates to an improvement in an electrical circuit device including a substrate of electrically insulating material having a first planar surface upon which is disposed an electrical circuit component;
an adjoining second generally planar surface angularly disposed relative to said first planar surface; said planar surfaces conjointly defining a line of intersection therebetween; an aperture extending inwardly from said second planar surface and having its entrance opening solely confined to said second planar surface; a terminal lead having a portion thereof seated within said aperture and having its remaining portion extending outwardly from said entrance opening; a conducting edge termination coating deposited transverse-ly of said second planar surface and extending from said aperture over said line of intersection and onto said first planar surface to pro~ide a continuous path between said electrical circuit component and said terminal lead; and a layer of conducting solder deposited on said edge termination coating; the combination therewith of an indentation formed in said substrate, said indentation traversing said line of intersection to communicate with each of said planar surfaces and underlying said deposited edge termination _ 3 _ ~' i ~51257 coating; whereby an uninterrupted conducting path of solder and its under-lying edge termination coating extends from said lead to connect with said electrical circuit component.
The present invention contemplates a method and means for improving and maintaining electrical conductivity in tfie edge termination layer deposited in one surface of a substrate and extending over an intersecting edge to an adjoining angularly disposed surface. The edge termination layer is of a conductive material intended to continue the circuit between electri-cal components supported by the substrate on the one surface and terminal leads extending outwardly from the adjoining surface. The material is compatible for electrical and mechanical connection with a solder layer deposited for retaining and anchoring the respective leads of the device.
The substrate may be made of a ceramic material, such as alumina or steatite, and is pressed or otherwise formed to include an indented area, which is the subject of the present invention. The indented - 3a -- B
. , .

~512~7 area may be in the form of a notch or an elongated groove inter-secting both of the adjoining surfaces. The groove is preferably formed in the substrate simultaneously with the pressing operation. It will be apparent, that when necessary, and with-S out departing from the invention, the groove or notch may be formedby abrasive,laser, or cutting operations after the substrate has been formed. The indented area provides a channel for in-suring adequate deposition of the edge termination material as it traverses the adjoining surfaces. This is comparable to providing a conducting "wire" running from a respective lead attached to one surface, from the lead, across the edge ter-mination surface supporting the lead, through the channel and onto the first-mentioned surface for electrical connection with circuitry supported by that surface.
Thus, any problems concerning leaching away of ter~.ination material during the soldering operations will be minimized by insuring adequate thickness of termination material as it extends from one surface across the relatively sharp edge or juncture between the adjoining surfaces.

Brief Description of the Drawings Fig. 1 is a perspective view of a single in-line packaging substrate suitable for use in the practice of the present invention;
Fig. 2 is a perspective view of the substrate of Fig. 1, illustrating the application of a layer of edge termination material extending from the edge surface and over onto a top surface relative to the view of Fig. 2;

Fig. 3 i5 a perspective view, including the edge ter-mination material underlying a typical rasistive network cir-cuit deposited on ~he upper surface of the substrate ofFigs. 1 and 2;

. llS1257 Fig. 4 is a perspectlve view of the finished product with a conformal coating applied thereto and termination leads mounted and soldered in place to provide a single in-line package;
Fig. 5 is a perspective view of a substrate provided for aual in-line packa~ing, and further arranged to incorporate the teachings of the present invention; and Fig. 6 is a perspective view, partly in section, illustrating a finished dual in-line package device in accordance with a second embodiment of this invention.

Description of the Preferred Embodiments An embodiment of the present invention is illustrated in the views of Figs. 1-4, inclusive. With reference to Fig. 1, it will be observed that a substrate 10 in the form of a parallelepiped is supplied to support electrical circuit com-ponents and terminal leads, as will hereinafter be described.The insulating substrate 10 is pressed, or otherwise formed, from a ceramic material, such as alumina or steatite, to pro-vide opposed upper and lower planar surfaces 11. Depending from, and angularly relative to, the planar surface 11 is a side or edge surface 12. This surface 12 is preferably planar and disposed normal to the surfaces 11.
Either one or both of the surfaces 11 may contain the electrical circuitry, which may be in the form of a network of resistors, a combination of resistors and capacitors and semiconductor chips, or chips of capacitors or the like. This circuit configuration is made in accordance with known techniques, and does not form a particular part of -the present invention.
The single in-line packaged (SIP) device presented ~y the views of Figs. 1-4, inclusive, has ~een previously disclosed and claimed in U.S. Patent No. 4,127,934, assigned to the same assignee as the present invention.

~SlZ5~
As was stated in that patent, the side or edge surface 12 includes a plurality of spaced apart openings 15 traversing the substrate 10 from the edge surface 12 all the way through to the opposite edge 13. These openings or apertures 15 are arranged to receive terminal leads, as will hereinafter be described.
For the purpose of spacing the edge surface 12 from a circuit board or other supporting means, the substrate 10 is provided with a pair of forwardly projecting standoffs 16 and 17.
Particular attention is drawn to the indentations in the form of grooves 18, which are formed in the edge wall 12, and which also indent inwardly of the planar s-urface 11. These indentations are an important part of the present invention, and will hereinafter be described in detail. For the present, it is important to note that the grooves may be "V" shaped as shown, or may be rounded off ~not shown) in a general "U" shape, or semicircular, where so desired. Although another embodiment will be described, the present embodiment is preferred at this time, since it is more facilely and inexpensively provided under known molding and pressing techniques. Although not specifi-cally shown, it will be apparent that the molding dies are moreeasily made to form the continuous groove 18 disposed for the entire length of the edge surface 12. The second embodiment illustrated in the views of Figs. 5 and 6 utilizes indentations in the form of notches, but the notches are necessarily small when compared to the elongated grooves 18. For instance, the presently described substrate has approximate overall dimensions of 0.78" x 0.30" x .08" with grooves 18 being only approxi-mately 0.01" wide at the outermost dimension. Obviously, notches are even smaller and the machining of pressing dies for forming this configuration is very detailed and complex.
With reference to Fig. 2, the substrate 10 is provided with edge termination areas 20. The areas 20 are transfer printed by means of a transfer wheel tnot shown) laying down a conducting material, such as silver paste, which extends across the face of the surface 12, and preferably a bit inwardly of the openings 15. The areas 20 also overlap the surface 11, as shown at 21. This overlapping area 21 connects the electrical circuitry to the edge of the substrate 10, as will later be explained. The material of the termination areas 20 (in this case silver paste) is well-known, and is compatible with solder for connecting to terminal leads. After application, the silver paste edge termination material 20 is fired on the substrate in the usual fashion.
Particular attention is drawn to the fact that the ter-mination material in the areas 20 nearly fills the grooves 18 to serve as a "wire-like" conductor passing from the holes or apertures 15 over and onto the overlapped areas 21 of the sur-face 11. This arrangementassures adequate thickness of the edge termination material. It is well-known that, although silver paste materials are ideal for serving as conductors and for compatibility with known solders, they also have the dis-advantage of tending to migrate into molten solder. The solder,as will later be explained, is deposited in automatic equipment, as fully described in the aforementioned ~artley et al related patents and represented by U.S. Patent No. 4,127,934, using wave solder baths and other known automatic t~chniques As much as the entire process of depositing the edge termination areas 20 and later described soldering techniques is intended to be fully automatic, slight variations in processing can lead to the application of a relatively ~hin layer at the line of intersection 25. This relatively .hin coat will ~end to leach away from the substrate and migrate in'o the later applied solder. The present invention therefore contemplate~ providing the "wire-like" conductive path to insure proper conductivity between the areas 20 and 21.

3 ~S~7 With reference to Fig. 3, it will be observed that a -~fpical resistive network may be laid down on the sur~ace 11 with known techniques utilizing thick or thin film material, such as the well-known cermet resistor materials, one of which is described in the Brandt et al U.S. Patent No. 3,639,274, assigned to the same assignee as the present invention. The particular com-position does not form a par~ of the present invention.
The resistive areas are denoted by the reference char acter 26, and in the case of cermet material, are screen printed or otherwise deposited to extend over the previously laid down conductive paths 27 which extend into and overlap the edge termination areas 21. Without going into the details of the circuitry, the conductive strips 27 are also of a glassy matrix, including highly conductive metallic materials inter-mixed therewith. The layers may be fired indiv.dually cr co-fired as desired. It is generally preferred to provide the conductive paths or layers 27 of material that resist adhesion to solder, to assist in preventing solder from adhering to portions of the substrate where it is unwanted. For this reason, it is also preferable to permit a small portion to slightly overlap the termination material 20 at the upper edge of the planar surface 12.
As illustrated in Fig. 4, leads 30 are inserted in each of the respective openings 15 in the manner disclosed and claimed in U.S. Patents No. 4,127,934, 4,187,529 and 4,213,113. As aforementioned, solder pads 31 are automatically applied by transporting the substrate 11, with theleads 30 attached thereto through a waveform solder bath (not shown). During this assembly process, the leads are preferably attachPd to a carrier strip o~ a lead frame (not sho~n) as disclosed in .he aforementioned patents.
It is preferred to provide a conformal coating 32 as a l~S~2S7 means of protecting the resistive and conductive layers 26 and 27, respectively, from the elements. Identification (not shown) may be printed directly to the conformally coated sur-face. The solder pads 31 serve to provide additional con-ductivity from the edge termination material at the areas 20and overlapping into the areas 21 to connect with the network.
The solder pads 31 act to also provide an additional anchoring means for the leads 30.
The embodiment of Figs. 5 and 6 illustrate another technique of providing the indented areas, which are the sub-~ect of the present invention. It will be apparent that either the grooved indentations illustrated in the views of Figs. 1-4, or the notches 35 may be utilized in either the SIP or the DIP devices with even facility. The two different devices, i.e. SIP and DIP, are merely shown as examples to indicate broad application of the present invention, which also may reside in various configurations of indented areas tra-versing between two adjoining planar surfaces, i.e. surfaces at 11 and 12 of the SIP construction of Figs. 1-4 and planar surfaces 36 and 37 defined by the line of intersection 38 of the substrate 40 of Figs. 5 and 6. The embodiment of Figs. 5 and 6 is explained in detail in the Beckman et al U.S. Patent No. 3,873,890, assigned to the same assignee as the present invention.
Suffice it to state that the dual in-line package con-struction of the device of Figs. 5 and 6 comprises a substrate 40 having a surface 36 arranged to receive a thick or thin film network 42 comprising a resistive layer 43 connected to leads 44 by means Gf conducting paths 45 overlyillg termination pads 46 which extend from the surface 35 over the line of intersection ~8 and onto the edge termination portion 47 of llSlZS7 the edge 37. Solder pads 48 are applied as described in con-nection with the discussion of the first embodiment. A con-formal coating 50 is later applied after the leads 44 have been anchored in place.
It will be observed that the notched areas extend between the planar surfaces 37 and 38 to provide a means of increasing the thickness of the edge termination coating overlapping both surfaces 36 and 37 and intersecting the line of intersection 38.
This wire-like conductive path assures adequate thickness of termination material to minimize the deleterious effects of "leaching" or migrating of silver into the solder as the solder is applied to retain the leads in place.
Although the invention herein has been specifically de-scribed in connection with devices having leads projecting from one or more sides of a substrate, it will also be understood that, such as in the case of certain hybrid circuits (not shown), the provision of the notches 35 or grooves 18 is equally appli-cable to devices which have no leads. In fact, the invention finds application in instances where solder is not applied.
The channels defined by the notches 35 or grooves 18 provide a ready means of assuring adequate "flow" during printing or other deposition of a layer, such as the edge termination areas or portions 21 and 46.

Claims (7)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. In an electrical circuit device including a sub-strate of electrically insulating material having a first planar surface upon which is disposed an electrical circuit component; an adjoining second generally planar surface angularly disposed relative to said first planar surface;
said planar surfaces conjointly defining a line of inter-section therebetween; an aperture extending inwardly from said second planar surface and having its entrance opening solely confined to said second planar surface; a terminal lead having a portion thereof seated within said aperture and having its remaining portion extending outwardly from said entrance opening; a conducting edge termination coating deposited transversely of said second planar surface and extending from said aperture over said line of intersection and onto said first planar surface to provide a continuous path between said electrical circuit component and said terminal lead; and a layer of conducting solder deposited on said edge termination coating: the combination therewith of an indentation formed in said substrate, said indentation traversing said line of intersection to communicate with each of said planar surfaces and underlying said deposited edge termination coating; whereby an uninterrupted conducting path of solder and its underlying edge termination coating extends from said lead to connect with said electrical circuit component.
2. The electrical circuit device of claim 1, wherein the said indentation is formed to provide a continuous groove communicating with said aperture, traversing the said second generally planar surface and intersecting the said first planar surface and the line of intersection defined by the adjoining planar surfaces.
3. The electrical circuit device of claim 1, wherein the said indenta-tion is formed to provide a notch intersecting each of the said planar surfaces and the edge defined by the adjoining planar surfaces.
4. The electrical circuit device of claim 1, wherein the said second planar surface supports a plurality of spaced apart termination leads, each of said leads in physical and electrical contact with a respective edge termination coating area, and a solder layer joining each termination coating area with its respective lead.
5. The electrical circuit device of claim 4, wherein the device provides a single in-line package with a plurality of transversely disposed, spaced apart openings extending through the substrate inwardly of the said second planar surface, and each opening arranged to receive and support a portion of respective termination lead with the remaining lead portion extending outwardly relative to the said second planar surface.
6. The electrical circuit device of claim 4, wherein the device provides a dual in-line package with a plurality of spaced apart cavities formed in oppositely opposed second planar surfaces adjoining said first planar surfaces, said cavities each arranged to receive and support respective termination leads.
7. A method of manufacturing an electrical circuit device, including the steps of:
forming a substrate of insulating material and having a circuit support planar surface and an adjoining, angular disposed, planar surface for supporting at least one termination lead and an indented area intersecting each of said surfaces and the edge defined by the said surface;
depositing a conducting termination coating area disposed transversely of one of said planar surfaces, said indented area and over-lapping a portion of said circuit supporting planar surface;
depositing a layer of electrical circuit components on said circuit supporting surface with conducting portions thereof being electrically connected to said termination coating and including the coated indented area;
providing at least one termination lead in supporting relationship with said lead supporting planar surface; and depositing a layer of solder on said lead and on the exposed surface of said conducting termination material.
CA000378327A 1980-08-25 1981-05-26 Edge termination for an electrical circuit device Expired CA1151257A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18132980A 1980-08-25 1980-08-25
US181,329 1980-08-25

Publications (1)

Publication Number Publication Date
CA1151257A true CA1151257A (en) 1983-08-02

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Family Applications (1)

Application Number Title Priority Date Filing Date
CA000378327A Expired CA1151257A (en) 1980-08-25 1981-05-26 Edge termination for an electrical circuit device

Country Status (5)

Country Link
JP (1) JPS5745962A (en)
CA (1) CA1151257A (en)
DE (1) DE3133584A1 (en)
FR (1) FR2489044A1 (en)
GB (1) GB2082843B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3406537A1 (en) * 1984-02-23 1985-08-29 Brown, Boveri & Cie Ag, 6800 Mannheim ARRANGEMENT OF A PERFORMANCE SEMICONDUCTOR COMPONENT ON AN INSULATING AND PROVIDED SUBSTRATE
GB2248345B (en) * 1990-09-27 1994-06-22 Stc Plc Edge soldering of electronic components
CN112074095B (en) * 2020-10-10 2021-08-31 黄石星河电路有限公司 Thin plate processing method with 0.4MM metal half-holes designed around

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3873890A (en) * 1973-08-20 1975-03-25 Allen Bradley Co Terminal construction for electrical circuit device
JPS5089874A (en) * 1973-12-12 1975-07-18
CA1055134A (en) * 1975-09-02 1979-05-22 Lawrence D. Radosevich Terminal lead construction for electrical circuit substrate

Also Published As

Publication number Publication date
FR2489044B3 (en) 1983-06-17
DE3133584A1 (en) 1982-07-01
GB2082843A (en) 1982-03-10
JPS5745962A (en) 1982-03-16
FR2489044A1 (en) 1982-02-26
GB2082843B (en) 1984-09-19

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