CA1099816A - Substrate bias voltage generated from refresh oscillator - Google Patents

Substrate bias voltage generated from refresh oscillator

Info

Publication number
CA1099816A
CA1099816A CA262,895A CA262895A CA1099816A CA 1099816 A CA1099816 A CA 1099816A CA 262895 A CA262895 A CA 262895A CA 1099816 A CA1099816 A CA 1099816A
Authority
CA
Canada
Prior art keywords
voltage
refresh
mos
memory
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA262,895A
Other languages
English (en)
French (fr)
Inventor
Edwin P. Fisher
Robert B. Johnson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1099816A publication Critical patent/CA1099816A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
CA262,895A 1975-11-28 1976-10-07 Substrate bias voltage generated from refresh oscillator Expired CA1099816A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/636,276 US4030084A (en) 1975-11-28 1975-11-28 Substrate bias voltage generated from refresh oscillator
US636,276 1975-11-28

Publications (1)

Publication Number Publication Date
CA1099816A true CA1099816A (en) 1981-04-21

Family

ID=24551206

Family Applications (1)

Application Number Title Priority Date Filing Date
CA262,895A Expired CA1099816A (en) 1975-11-28 1976-10-07 Substrate bias voltage generated from refresh oscillator

Country Status (6)

Country Link
US (1) US4030084A (US06397114-20020528-M00001.png)
JP (1) JPS5267533A (US06397114-20020528-M00001.png)
BE (1) BE848031A (US06397114-20020528-M00001.png)
CA (1) CA1099816A (US06397114-20020528-M00001.png)
FR (1) FR2333296A1 (US06397114-20020528-M00001.png)
GB (1) GB1514869A (US06397114-20020528-M00001.png)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4130899A (en) * 1977-11-25 1978-12-19 Ncr Corporation System for operating volatile memory in normal and standby modes
JPS5559756A (en) * 1978-10-30 1980-05-06 Fujitsu Ltd Semiconductor device
DE2853925A1 (de) * 1978-12-14 1980-07-03 Bosch Gmbh Robert Bordrechner fuer kraftfahrzeuge
JPS55162257A (en) * 1979-06-05 1980-12-17 Fujitsu Ltd Semiconductor element having substrate bias generator circuit
JPS5619676A (en) * 1979-07-26 1981-02-24 Fujitsu Ltd Semiconductor device
JPS5683057A (en) * 1979-12-11 1981-07-07 Nec Corp Integrated circuit
JPS5694654A (en) * 1979-12-27 1981-07-31 Toshiba Corp Generating circuit for substrate bias voltage
JPS56117390A (en) * 1980-02-16 1981-09-14 Fujitsu Ltd Semiconductor memory device
DE3009303A1 (de) * 1980-03-11 1981-09-24 Siemens AG, 1000 Berlin und 8000 München Monolithisch integrierte digitale halbleiterschaltung
JPS59162690A (ja) * 1983-03-04 1984-09-13 Nec Corp 擬似スタテイツクメモリ
US5125077A (en) * 1983-11-02 1992-06-23 Microsoft Corporation Method of formatting data from a mouse
JPS60136157U (ja) * 1984-12-29 1985-09-10 富士通株式会社 半導体記憶装置
KR940008147B1 (ko) * 1991-11-25 1994-09-03 삼성전자 주식회사 저전력 데이타 리텐션 기능을 가지는 반도체 메모리장치
US5596534A (en) * 1995-06-27 1997-01-21 Micron Technology, Inc. Circuit including DRAM and voltage regulator, and method of increasing speed of operation of a DRAM

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3651494A (en) * 1970-03-27 1972-03-21 Sperry Rand Corp Ferroelectric synchronizing and integrating apparatus
US3806741A (en) * 1972-05-17 1974-04-23 Standard Microsyst Smc Self-biasing technique for mos substrate voltage
US3760380A (en) * 1972-06-02 1973-09-18 Motorola Inc Silicon gate complementary mos dynamic ram
US3795898A (en) * 1972-11-03 1974-03-05 Advanced Memory Syst Random access read/write semiconductor memory
GB1462935A (en) * 1973-06-29 1977-01-26 Ibm Circuit arrangement
US3870901A (en) * 1973-12-10 1975-03-11 Gen Instrument Corp Method and apparatus for maintaining the charge on a storage node of a mos circuit

Also Published As

Publication number Publication date
BE848031A (US06397114-20020528-M00001.png) 1977-03-01
JPS5267533A (en) 1977-06-04
GB1514869A (en) 1978-06-21
FR2333296B1 (US06397114-20020528-M00001.png) 1983-02-11
FR2333296A1 (fr) 1977-06-24
US4030084A (en) 1977-06-14

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Legal Events

Date Code Title Description
MKEX Expiry