CA1082373A - Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps - Google Patents

Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps

Info

Publication number
CA1082373A
CA1082373A CA273,411A CA273411A CA1082373A CA 1082373 A CA1082373 A CA 1082373A CA 273411 A CA273411 A CA 273411A CA 1082373 A CA1082373 A CA 1082373A
Authority
CA
Canada
Prior art keywords
substrate
layer
aperture
upper layer
bottom layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA273,411A
Other languages
English (en)
French (fr)
Inventor
Conrad A. Barile
Robert M. Brill
John L. Forneris
Joseph Regh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1082373A publication Critical patent/CA1082373A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/143—Shadow masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/965—Shaped junction formation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)
  • Formation Of Insulating Films (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
CA273,411A 1976-04-05 1977-03-08 Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps Expired CA1082373A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/673,314 US4060427A (en) 1976-04-05 1976-04-05 Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps
US673,314 1976-04-05

Publications (1)

Publication Number Publication Date
CA1082373A true CA1082373A (en) 1980-07-22

Family

ID=24702144

Family Applications (1)

Application Number Title Priority Date Filing Date
CA273,411A Expired CA1082373A (en) 1976-04-05 1977-03-08 Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps

Country Status (12)

Country Link
US (1) US4060427A (US20100268047A1-20101021-C00003.png)
JP (1) JPS6025894B2 (US20100268047A1-20101021-C00003.png)
AU (1) AU504131B2 (US20100268047A1-20101021-C00003.png)
BE (1) BE851929A (US20100268047A1-20101021-C00003.png)
CA (1) CA1082373A (US20100268047A1-20101021-C00003.png)
DE (1) DE2707693C3 (US20100268047A1-20101021-C00003.png)
FR (1) FR2347778A1 (US20100268047A1-20101021-C00003.png)
GB (1) GB1516292A (US20100268047A1-20101021-C00003.png)
IT (1) IT1118012B (US20100268047A1-20101021-C00003.png)
NL (1) NL7703632A (US20100268047A1-20101021-C00003.png)
SE (1) SE7702443L (US20100268047A1-20101021-C00003.png)
ZA (1) ZA771835B (US20100268047A1-20101021-C00003.png)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4131497A (en) * 1977-07-12 1978-12-26 International Business Machines Corporation Method of manufacturing self-aligned semiconductor devices
US4119446A (en) * 1977-08-11 1978-10-10 Motorola Inc. Method for forming a guarded Schottky barrier diode by ion-implantation
US4149904A (en) * 1977-10-21 1979-04-17 Ncr Corporation Method for forming ion-implanted self-aligned gate structure by controlled ion scattering
FR2417909A1 (fr) * 1978-02-17 1979-09-14 Thaille Jean Louis Regulateur de pression (ou charge) acoustique
US4176029A (en) * 1978-03-02 1979-11-27 Sperry Rand Corporation Subminiature bore and conductor formation
US4263603A (en) * 1978-03-02 1981-04-21 Sperry Corporation Subminiature bore and conductor formation
US4157269A (en) * 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques
US4262399A (en) * 1978-11-08 1981-04-21 General Electric Co. Ultrasonic transducer fabricated as an integral park of a monolithic integrated circuit
US4199380A (en) * 1978-11-13 1980-04-22 Motorola, Inc. Integrated circuit method
US4198250A (en) * 1979-02-05 1980-04-15 Intel Corporation Shadow masking process for forming source and drain regions for field-effect transistors and like regions
DE2917455A1 (de) * 1979-04-30 1980-11-13 Ibm Deutschland Verfahren zur vollstaendigen ausheilung von gitterdefekten in durch ionenimplantation von phosphor erzeugten n-leitenden zonen einer siliciumhalbleitervorrichtung und zugehoerige siliciumhalbleitervorrichtung
US4371423A (en) * 1979-09-04 1983-02-01 Vlsi Technology Research Association Method of manufacturing semiconductor device utilizing a lift-off technique
US4309812A (en) * 1980-03-03 1982-01-12 International Business Machines Corporation Process for fabricating improved bipolar transistor utilizing selective etching
US4318751A (en) * 1980-03-13 1982-03-09 International Business Machines Corporation Self-aligned process for providing an improved high performance bipolar transistor
US4334348A (en) * 1980-07-21 1982-06-15 Data General Corporation Retro-etch process for forming gate electrodes of MOS integrated circuits
JPS5870570A (ja) * 1981-09-28 1983-04-27 Fujitsu Ltd 半導体装置の製造方法
JPH0654778B2 (ja) * 1985-04-23 1994-07-20 株式会社東芝 半導体装置及びその製造方法
JPS6393153A (ja) * 1986-10-07 1988-04-23 Toshiba Corp 半導体装置の製造方法
US5098851A (en) * 1989-02-10 1992-03-24 Hitachi, Ltd. Fabricating a semiconductor photodetector by annealing to smooth the PN junction
US5244821A (en) * 1991-06-07 1993-09-14 At&T Bell Laboratories Bipolar fabrication method
US5766695A (en) * 1996-11-27 1998-06-16 Hughes Electronics Corporation Method for reducing surface layer defects in semiconductor materials having a volatile species
US6331468B1 (en) * 1998-05-11 2001-12-18 Lsi Logic Corporation Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers
JP2000040691A (ja) * 1998-07-21 2000-02-08 Oki Electric Ind Co Ltd 半導体装置製造方法
US8791546B2 (en) * 2010-10-21 2014-07-29 Freescale Semiconductor, Inc. Bipolar transistors having emitter-base junctions of varying depths and/or doping concentrations
CN112053952B (zh) * 2019-06-05 2022-02-11 上海先进半导体制造有限公司 高耐压大电流增益的衬底pnp晶体管及其制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE756040A (fr) * 1969-09-15 1971-02-15 Western Electric Co Procede pour former, par implantation d'ions, une zone localisee dans un corps de semi-conducteur
DE1952632A1 (de) * 1969-10-18 1971-04-22 Licentia Gmbh Verfahren zum Herstellen einer Diffusionszone
US3717790A (en) * 1971-06-24 1973-02-20 Bell Telephone Labor Inc Ion implanted silicon diode array targets for electron beam camera tubes
US3764423A (en) * 1972-03-15 1973-10-09 Bell Telephone Labor Inc Removal of dielectric ledges on semiconductors
JPS5242842B2 (US20100268047A1-20101021-C00003.png) * 1972-09-05 1977-10-27
US3947866A (en) * 1973-06-25 1976-03-30 Signetics Corporation Ion implanted resistor having controlled temperature coefficient and method
DE2341154C2 (de) * 1973-08-14 1975-06-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer Zweiphasen-Ladungsverschiebeanordnung
JPS50120257A (US20100268047A1-20101021-C00003.png) * 1974-03-05 1975-09-20

Also Published As

Publication number Publication date
GB1516292A (en) 1978-07-05
BE851929A (fr) 1977-06-16
AU2365277A (en) 1978-09-28
FR2347778B1 (US20100268047A1-20101021-C00003.png) 1978-10-20
ZA771835B (en) 1978-11-29
NL7703632A (nl) 1977-10-07
JPS6025894B2 (ja) 1985-06-20
SE7702443L (sv) 1977-10-06
AU504131B2 (en) 1979-10-04
JPS52122470A (en) 1977-10-14
DE2707693B2 (de) 1978-12-07
DE2707693A1 (de) 1977-10-06
US4060427A (en) 1977-11-29
DE2707693C3 (de) 1979-08-16
FR2347778A1 (fr) 1977-11-04
IT1118012B (it) 1986-02-24

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