CA1045716A - Method for operating transistor storage flip-flop and evaluator circuit therefor - Google Patents
Method for operating transistor storage flip-flop and evaluator circuit thereforInfo
- Publication number
- CA1045716A CA1045716A CA196,877A CA196877A CA1045716A CA 1045716 A CA1045716 A CA 1045716A CA 196877 A CA196877 A CA 196877A CA 1045716 A CA1045716 A CA 1045716A
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- CA
- Canada
- Prior art keywords
- flip
- transistor
- circuit
- digit line
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
Abstract
A fire-transistor storage element comprising a storage flip-flop circuit and a selector transistor connected to a node thereof and to a digit line, with the selector transistor being controlled over a word line connected to its gate, which storage element is read-out by means of an evaluator circuit having two operable states, corresponding to those of the storage flip-flop circuit, and method of operating the same, in which the capacitance of the digit line is charged, prior to commencement of the read-out cycle, to a predetermined voltage which corresponds approximately to the voltage occurring across the loaded node of the storage flip-flop circuit when the latter is at its labile point, adjusting the voltage across the capacitance of the digit line in accordance with the data stored in the store element by switching the selector transistor conductive, to thereby set the evaluator circuit into the state corresponding to the stored data, and, during write-in, applying to the digit line a predetermined voltage corresponding to the data to be written in, as a result of which the storage flip-flop circuit is brought into the desired state when the select- or transistor is conductive.
Description
~6~457~6 The invention is directed to an evaluator circuit for reading and writing digital information out of and into a transistor storage flip-flop circuit with an individually associated selector transistor and a method for effecting write-in and read-out of data in such a storage element, wherein the storage structure or element contains a storage flip-flop circuit and a selector transistor, with the storage element being connected over a digit line to an evaluator circuit.
When five-transistor storage elements are employed, four trans-istors of which form a storage flip-flop circuit and the fifth functions as a selector transistor, it is necessary, prior to the commencement of the read-out process, to bring the voltage on the digit line, which is connected to individual storage elements, approximately to the level which occurs at :;:
the nodal point of the storage element when the latter is maintained at the :
labile point.
It is the objective of the invention to provide an evaluator circuit for a transistor storage flip-flop circuit with an individually associated selector transistor and a method for the operation of such storage flip-flop, by means of which the voltage on the digit line is balanced to the voltage which exists at the nodal point of a storage element when at the labile point.
According to one aspect of the invention there is provided an evaulator circuit for reading and writing digital information out of and into a transistor storage flip-flop circuit with an individually associated selector transistor and having two operable states, corresponding to those : of the storage flip-flop circuit, said evaluator circuit having an input connected to a digit line of the storage flip-flop circuit, and an output, and a shunt transistor operatively connecting the input and the output of the evaluator circuit, the gate of which controls the application of voltage at the output of the evaluator circuit to said digit line.
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S'716 The evaluator circuit is particularly useful with a five-transistor storage structure in the complementary-channel MOS technique, comprising a four-transistor storage flip-flop circuit~ and a selector transistor operatively connecting a node of the flip-flop circuit to a digit line, and a word line connected to the gate of the selector transistor for controlling the operation thereof, the Mip-flop circuit being symmetrical in relation to the node to which the selector transistor is connected.
The five-transistor storage element is read-out in conjunction with the evaluator circuit, which mày~also be constructed in complementary lo channel - MOS - technique. In accordance with the method of the invention, there is provided a method for the operation of a transistor storage flip-flop element comprising a storage flip-flop circuit and a selector transistor connected to a node thereof and to a digit line having a capaci-tance against ground, with the selector transistor being controlled over a word line :
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connected to its gate, which storage element is read out by means of an evaluator circuit having two operable states, eorresponding to those of the storage flip-flop circuit, comprising the steps of charging the cap-acitance of the digit line, prior to eommencement of the read-out cycle, to a predetermined voltage which corresponds approximately to the voltage which occurs across the node of the storage flip flop circuit which is connected to the selector transistor, when the storage flip-flop circuit is in its labile point, thereafter switehing the seleetor transistor of the storage element conductive, whereby the voltage across the capacitance of the digit line is adjusted in accordance with the data stored in the storage element, to thereby set the evaluator circuit, as a result of the voltage change on the digit line, into the state corresponding to the stored data, and, during write-in, applying to the digit line a predetermined voltage corresponding to the data to be written in, as a result of which the storage flip-flop is brought into such a state when the selector transistor is conductive.
A particular advantage of the method aceording to the invention eonslsts in the faet that the data ean be written into a five-transistor storage element and read out thereof without incurring any substantial loss in speed as a result of the recharging of the digit line, and without des-truction of the data stored.
Advantageously, a storage arrangement containing five-transistor storage elements is approximately 30% smaller than the same general arrange-ment employing six-transistor storage elements.
In aceordanee with a further feature of the invention, the evalu-ator eireuit may be in the form of an inverter stage, also eonstrueted in eomplementary ehannel - MOS - teehnique, in which the input is eonnected to the digit line, and the input and output of the stage are eonnected to one another over a shunt transistor whieh is switehed eonduetive over a
When five-transistor storage elements are employed, four trans-istors of which form a storage flip-flop circuit and the fifth functions as a selector transistor, it is necessary, prior to the commencement of the read-out process, to bring the voltage on the digit line, which is connected to individual storage elements, approximately to the level which occurs at :;:
the nodal point of the storage element when the latter is maintained at the :
labile point.
It is the objective of the invention to provide an evaluator circuit for a transistor storage flip-flop circuit with an individually associated selector transistor and a method for the operation of such storage flip-flop, by means of which the voltage on the digit line is balanced to the voltage which exists at the nodal point of a storage element when at the labile point.
According to one aspect of the invention there is provided an evaulator circuit for reading and writing digital information out of and into a transistor storage flip-flop circuit with an individually associated selector transistor and having two operable states, corresponding to those : of the storage flip-flop circuit, said evaluator circuit having an input connected to a digit line of the storage flip-flop circuit, and an output, and a shunt transistor operatively connecting the input and the output of the evaluator circuit, the gate of which controls the application of voltage at the output of the evaluator circuit to said digit line.
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,, . .. . , -..~
.:
S'716 The evaluator circuit is particularly useful with a five-transistor storage structure in the complementary-channel MOS technique, comprising a four-transistor storage flip-flop circuit~ and a selector transistor operatively connecting a node of the flip-flop circuit to a digit line, and a word line connected to the gate of the selector transistor for controlling the operation thereof, the Mip-flop circuit being symmetrical in relation to the node to which the selector transistor is connected.
The five-transistor storage element is read-out in conjunction with the evaluator circuit, which mày~also be constructed in complementary lo channel - MOS - technique. In accordance with the method of the invention, there is provided a method for the operation of a transistor storage flip-flop element comprising a storage flip-flop circuit and a selector transistor connected to a node thereof and to a digit line having a capaci-tance against ground, with the selector transistor being controlled over a word line :
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....:
~457~
connected to its gate, which storage element is read out by means of an evaluator circuit having two operable states, eorresponding to those of the storage flip-flop circuit, comprising the steps of charging the cap-acitance of the digit line, prior to eommencement of the read-out cycle, to a predetermined voltage which corresponds approximately to the voltage which occurs across the node of the storage flip flop circuit which is connected to the selector transistor, when the storage flip-flop circuit is in its labile point, thereafter switehing the seleetor transistor of the storage element conductive, whereby the voltage across the capacitance of the digit line is adjusted in accordance with the data stored in the storage element, to thereby set the evaluator circuit, as a result of the voltage change on the digit line, into the state corresponding to the stored data, and, during write-in, applying to the digit line a predetermined voltage corresponding to the data to be written in, as a result of which the storage flip-flop is brought into such a state when the selector transistor is conductive.
A particular advantage of the method aceording to the invention eonslsts in the faet that the data ean be written into a five-transistor storage element and read out thereof without incurring any substantial loss in speed as a result of the recharging of the digit line, and without des-truction of the data stored.
Advantageously, a storage arrangement containing five-transistor storage elements is approximately 30% smaller than the same general arrange-ment employing six-transistor storage elements.
In aceordanee with a further feature of the invention, the evalu-ator eireuit may be in the form of an inverter stage, also eonstrueted in eomplementary ehannel - MOS - teehnique, in which the input is eonnected to the digit line, and the input and output of the stage are eonnected to one another over a shunt transistor whieh is switehed eonduetive over a
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~3457~L6 puLse train line prior to the commencement of the read-out cycle, as a result of which the desired voltage is applied to the digit line. Upon a voltage change on the digit line, in accordance with data stored in the storage element, and blockage of the shu~t transistor, an electrical signal will be present at the output of the inverter stage, corresponding to the full voltage range of the supply voltage of such stage. Equal supply voltages are provided across the storage element and across the inverter stage with . ~ , -2a-- . .
. ., ~
. . . - . :. ~ - ,. ..
~3457~L6 puLse train line prior to the commencement of the read-out cycle, as a result of which the desired voltage is applied to the digit line. Upon a voltage change on the digit line, in accordance with data stored in the storage element, and blockage of the shu~t transistor, an electrical signal will be present at the output of the inverter stage, corresponding to the full voltage range of the supply voltage of such stage. Equal supply voltages are provided across the storage element and across the inverter stage with . ~ , -2a-- . .
3~57~6 the transistors of the inverter stage of the evaluator circuit being so dimensioned that the desired voltage is provided when the shunt transistor is conductive. Advantageously such an evaluator circuit may comprise merely three transistors.
In accordance with a further development of the invention, the evaluator circuit may take the form of a flip-flop circuit in which one node of the flip-flop is connected to the digit line and the two nodes of the flip-flop are connected over a shunt transistor. In this case the shunt transistor is switched conductive prior to the commencement of the read-out cycle, and with a voltage change corresponding to the item of data stored in the storage element occurring on the digit line, and blockage of the shunt transistor, the flip-flop will be se~ into a state corresponding to the data, which state corresponds to a stable point of the flip-flop circuit. For writing-in, two address transistors, associated with the evaluator flip-flop circuit are switched conductive over common gate terminals. The transistors of the evaluator flip-flop circuit are dimensioned in such a manner that the desired voltage is provided when the shunt transistor is conductive, assum-ing equal supply voltages across the storage element and across the eval-uator flip-flop circuit. Such type of evaluator circuit provides the advan-tage of a greater speed and greater sensitivity.
In the drawings wherein like reference characters indicate like or corresponding parts:-FIGURE 1 is a schematic diagram illustrating the circuit of a five-transistor storage element and an evaluator circuit employing an in-verter stage;
FIGURE 2 is a graph illustrating the dependence of the current, 1, flowing through the selector transistor of a storage element, upon the voltage U across the nodal point;
FIGURE 3 is a graph schematically illustrating the characteristic ~q~57~6 curve of an inverter stage; and FIGURE 4 is a schematic diagram similar to Figure 1, illustrating a circuit comprising a five-transistor storage element and an evaluator circuit employing a flip-flop circuit.
Referring to Figure 1, the reference numeral 2 indicates generally a five-transistor storage element, which is in the form of a flip-flop circuit, composed of transistors 21, 22, 23 and 25, with transistors 22 and 23 being cross-connected with resistors 21 and 25. The supply voltage UB is operatively connected between points 27 and 28 of such flip-flop circuit, with point 27, for example, being connected to ground. The node 29 of the flip-flop circuit is connected to the digit line 3 over a selector transistor 26 which also forms a part of the five-transistor storage element 2, the gate of such transistor being operated over the word line 8.
Advantageously, the flip-flop circuit is so designed that it is electrically symmetrical in relation to the node 29 to which the selector transistor 26 is connected, whereby the labile point of the flip-flop circuit corresponds to exactly half the supply voltage.
The evaluator circuit 1 is likewise connected to the digit line 3, and in the embodiment illustrated comprises transistors 11, 12 and 13, with the transistors 11 and 12 being connected in series and the supply voltage of the inverter stage being applied to terminal points 14 and 15, with the l~t point ~, in the example illustrated, being connected to ground. The gate terminals of transistors 11 and 12 are connected, in common, to terminal point 17 which represents the input of the evaluator circuit and which is connected to the digit line 3. Terminal point 16 represents the output of the evaluation circuit and is operatively connectible with the input 17 thereof over the shunt transistor 13. Operation of the latter is controlled by its gate which is connected to a pulse train line 5, while the output 16 of the evaluator circuit is connected to the read-out line 6 over an address ~4S7~6 transistor 4, the gate of which is controlled over the terminal ~1.
The digit line 3 is also connected over an address transistor 32 to a write-in line 7, with the transistor 32 being controlled by its gate which is connected to terminal 321.
As mentioned, both the storage element 2 and the evaluator circuit ~-1 are constructed in a complementary channel - MOS - technique, preferably upon an insulating substrate.
Read-out of data from the storage element 2 over the evaluator circuit 1, connected to the digit line 3, is as follows: Prior to commen-cement of the read-out cycle, the transistor 13 is actuated to conductive state over the line 5, as a result of which the input 17 of the inverter stage is connected to the output 16 thereof. This in turn results in the application of a predetermined voltage, corresponding to the voltage across the node 29 of the storage flip-Plop when the latter is at the labile point, being applied over the input 17 to the digit line, as a result of which the capacitance of the digit line is charged to such voltage, such capacitance being schematically illustrated in Figure 1 and designatsd by the reference numeral 31. If the storage element 2 is selected over the word line 8 as a result of the transistor 26 being actuated to conductive state, a voltage change corresponding to the data stored in the storage element will be pro-duced across the capacitance 31 of the digit line. This voltage change, in turn, when the shunt transistor 13 is blocked, produces a signal voltage across the output 16 of the inverter stage, corresponding to the full voltage range of the supply voltage.
Figure 2 schematically illustrates the characteristic curve 81, 82 of the storage flip-flop circuit and additionally illustrates the operative curve 84 during read-out and the operative curves 83, 85 during write-in.
The voltage connected to the nodal point 29 of the storage element is plotted on the X-axis and the current flowing into the storage element 2 on the . .
~57~L6 Y-axis. Initially, during the read-out process, as previously above descri-bed, the digit line carries a predetermined voltage which here corresponds approximately to half the supply voltage, i.e. corresponds to point UB/2 in Figure 2.
Depending upon the nature of the data stored in the flip-flop circuit, the capacitance of the digit line 3 will be charged, either to the supply voltage UB or discharged to the voltage 0. The charging of the capa-citance of the digit line to the supply voltage UB, which is governed by the curve portion 81 corresponds to a read-out of a ~ l while the discharge of the capacitance of the digit line to the voltage 0, which is governed by the curve portion 82, corresponds to the read-out of a "0".
As a result of the effective utili~ation of the amplification of the inverter stage, even a small voltage change on the digit line 3 will be sufficient to obtain a signal voltage, corresponding to the full supply vol-tage, at the output of the in~erter stage. Figure 3 illustrates the depend-ence of the voltage Ua occurring at the output of the inverter stage upon the voltage Ue occurring at the input of the inverter stage. The signal appearing at the output 16 of the inverter stage preferably is read-out over the address transistor 4.
To effect a write-in of data into the storage element 2, a voltage, corresponding to the item of data to be written in, is applied over address transistor 32 to the digit line 3, and conducted to the flip-flop circuit of the storage element when the transistor 26 is conductive, whereby flip-flop circuit is set in the appropriate state in accordance with the particular item of data to be stored. This is illustrated in Figure 2 by the character-istic curves 83, 85.
In accordance with a further feature of the invention, in the em-bodiment illustrated in Figure 4, the evaluator circuit is in the form of a flip-flop circuit comprising transistors 91, 92, 93 and 94, along with a shunt transistor 95, with a supply voltage UB being applied between the points 96 and 97 of the flip-flop, of which the point 96 is illustrated, for example, as being connected to ground. The nodes 98 and 99 of the flip-flop circuit are adapted to be connected to each other over the shunt transistor 95 which may be actuated over the pulse train line 71.
In the read-out of data, the transistor 95 initially is rendered conductive, as a result of which the flip-flop is set in its labile point and the digit line is thereby brought to approximately half the operating voltage (Figure 2~. Upon the selector transistor of the storage element 2 being brought into a conductive state, as previously described in connection with the circuit of Figure 1, with the aid of the current I flowing into and out of the storage element, the flip-flop circuit of the evaluator circuit is brought into a state corresponding to the stored item of data. In Figure 2, this current corresponds approximately to the current IL ~~ or the current IL "1". When the shunt transistor 95 is blocked (disconnected), as a result of the read-out current from the storage element, the evaluator flip- ~`
flop circuit will flip into the state corresponding to the stored data, which state corresponds to one of the stable points of the flip-flop circuit.
For effecting the ~ite-in of data the voltage, corresponding to the item of data to be written-in, is conducted over two transistors 42, 43, the gates of which are connected in common to the terminal 411, to the evaluator flip-flop circuit and thus, over the digit line, to the storage element. This is schematically illustra-ted in Figure 2 by the characteristic curves 83, 85, respectively. The use of a flip-flop circuit as the evaluator circuit results in the advantage of a greater speed and greater sensitivity.
It will particularly be noted, with respect to the resistance of ; the circuit to errors, that the digit line is brought approximately to the voltage which would exist at the nodal point of the storage element when it is in the labile point, which condition can be fulfilled relatively accurately ' .
1¢J 45~6 if, in the exemplary embodiment illustrated in Figure 1, the inverter stage of the evaluator circuit 1 is designed to be proportional to the controlling arm of the storage flip-flop circuit and in the circuit of Figure ~, the evaluator flip-flop is designed to be proportional to the storage flip-flop.
The term "proportional" as here utilized is to be understood to mean that the ratio of the quotients of channel width and channel length in the correspond-ing transistors is equal. In the exemplary embodiment illustrated in Figure 1, the transistors 11, 12 of the inverter stage correspond to the transistors 23, 22 respectively of the storage element and in the example of Figure 4, the transistors 91, 92, 93 and 94 of the evaluator flip-flop circuit corres-pond to the transistors 22, 23, 21 and 25 of the storage element.
In both of such cases the above mentioned condition can be accur-; ately fulfilled in the absence o deviation of the parameters of the chip.
; Having thus described our invention it will be obvious that although various minor modifications might be suggested by those versed in the art, it should be understood that we wish to embody within the scope of the patent granted hereon all such modifications as reasonably, and properly come within the scope of our contribution to the art.
In accordance with a further development of the invention, the evaluator circuit may take the form of a flip-flop circuit in which one node of the flip-flop is connected to the digit line and the two nodes of the flip-flop are connected over a shunt transistor. In this case the shunt transistor is switched conductive prior to the commencement of the read-out cycle, and with a voltage change corresponding to the item of data stored in the storage element occurring on the digit line, and blockage of the shunt transistor, the flip-flop will be se~ into a state corresponding to the data, which state corresponds to a stable point of the flip-flop circuit. For writing-in, two address transistors, associated with the evaluator flip-flop circuit are switched conductive over common gate terminals. The transistors of the evaluator flip-flop circuit are dimensioned in such a manner that the desired voltage is provided when the shunt transistor is conductive, assum-ing equal supply voltages across the storage element and across the eval-uator flip-flop circuit. Such type of evaluator circuit provides the advan-tage of a greater speed and greater sensitivity.
In the drawings wherein like reference characters indicate like or corresponding parts:-FIGURE 1 is a schematic diagram illustrating the circuit of a five-transistor storage element and an evaluator circuit employing an in-verter stage;
FIGURE 2 is a graph illustrating the dependence of the current, 1, flowing through the selector transistor of a storage element, upon the voltage U across the nodal point;
FIGURE 3 is a graph schematically illustrating the characteristic ~q~57~6 curve of an inverter stage; and FIGURE 4 is a schematic diagram similar to Figure 1, illustrating a circuit comprising a five-transistor storage element and an evaluator circuit employing a flip-flop circuit.
Referring to Figure 1, the reference numeral 2 indicates generally a five-transistor storage element, which is in the form of a flip-flop circuit, composed of transistors 21, 22, 23 and 25, with transistors 22 and 23 being cross-connected with resistors 21 and 25. The supply voltage UB is operatively connected between points 27 and 28 of such flip-flop circuit, with point 27, for example, being connected to ground. The node 29 of the flip-flop circuit is connected to the digit line 3 over a selector transistor 26 which also forms a part of the five-transistor storage element 2, the gate of such transistor being operated over the word line 8.
Advantageously, the flip-flop circuit is so designed that it is electrically symmetrical in relation to the node 29 to which the selector transistor 26 is connected, whereby the labile point of the flip-flop circuit corresponds to exactly half the supply voltage.
The evaluator circuit 1 is likewise connected to the digit line 3, and in the embodiment illustrated comprises transistors 11, 12 and 13, with the transistors 11 and 12 being connected in series and the supply voltage of the inverter stage being applied to terminal points 14 and 15, with the l~t point ~, in the example illustrated, being connected to ground. The gate terminals of transistors 11 and 12 are connected, in common, to terminal point 17 which represents the input of the evaluator circuit and which is connected to the digit line 3. Terminal point 16 represents the output of the evaluation circuit and is operatively connectible with the input 17 thereof over the shunt transistor 13. Operation of the latter is controlled by its gate which is connected to a pulse train line 5, while the output 16 of the evaluator circuit is connected to the read-out line 6 over an address ~4S7~6 transistor 4, the gate of which is controlled over the terminal ~1.
The digit line 3 is also connected over an address transistor 32 to a write-in line 7, with the transistor 32 being controlled by its gate which is connected to terminal 321.
As mentioned, both the storage element 2 and the evaluator circuit ~-1 are constructed in a complementary channel - MOS - technique, preferably upon an insulating substrate.
Read-out of data from the storage element 2 over the evaluator circuit 1, connected to the digit line 3, is as follows: Prior to commen-cement of the read-out cycle, the transistor 13 is actuated to conductive state over the line 5, as a result of which the input 17 of the inverter stage is connected to the output 16 thereof. This in turn results in the application of a predetermined voltage, corresponding to the voltage across the node 29 of the storage flip-Plop when the latter is at the labile point, being applied over the input 17 to the digit line, as a result of which the capacitance of the digit line is charged to such voltage, such capacitance being schematically illustrated in Figure 1 and designatsd by the reference numeral 31. If the storage element 2 is selected over the word line 8 as a result of the transistor 26 being actuated to conductive state, a voltage change corresponding to the data stored in the storage element will be pro-duced across the capacitance 31 of the digit line. This voltage change, in turn, when the shunt transistor 13 is blocked, produces a signal voltage across the output 16 of the inverter stage, corresponding to the full voltage range of the supply voltage.
Figure 2 schematically illustrates the characteristic curve 81, 82 of the storage flip-flop circuit and additionally illustrates the operative curve 84 during read-out and the operative curves 83, 85 during write-in.
The voltage connected to the nodal point 29 of the storage element is plotted on the X-axis and the current flowing into the storage element 2 on the . .
~57~L6 Y-axis. Initially, during the read-out process, as previously above descri-bed, the digit line carries a predetermined voltage which here corresponds approximately to half the supply voltage, i.e. corresponds to point UB/2 in Figure 2.
Depending upon the nature of the data stored in the flip-flop circuit, the capacitance of the digit line 3 will be charged, either to the supply voltage UB or discharged to the voltage 0. The charging of the capa-citance of the digit line to the supply voltage UB, which is governed by the curve portion 81 corresponds to a read-out of a ~ l while the discharge of the capacitance of the digit line to the voltage 0, which is governed by the curve portion 82, corresponds to the read-out of a "0".
As a result of the effective utili~ation of the amplification of the inverter stage, even a small voltage change on the digit line 3 will be sufficient to obtain a signal voltage, corresponding to the full supply vol-tage, at the output of the in~erter stage. Figure 3 illustrates the depend-ence of the voltage Ua occurring at the output of the inverter stage upon the voltage Ue occurring at the input of the inverter stage. The signal appearing at the output 16 of the inverter stage preferably is read-out over the address transistor 4.
To effect a write-in of data into the storage element 2, a voltage, corresponding to the item of data to be written in, is applied over address transistor 32 to the digit line 3, and conducted to the flip-flop circuit of the storage element when the transistor 26 is conductive, whereby flip-flop circuit is set in the appropriate state in accordance with the particular item of data to be stored. This is illustrated in Figure 2 by the character-istic curves 83, 85.
In accordance with a further feature of the invention, in the em-bodiment illustrated in Figure 4, the evaluator circuit is in the form of a flip-flop circuit comprising transistors 91, 92, 93 and 94, along with a shunt transistor 95, with a supply voltage UB being applied between the points 96 and 97 of the flip-flop, of which the point 96 is illustrated, for example, as being connected to ground. The nodes 98 and 99 of the flip-flop circuit are adapted to be connected to each other over the shunt transistor 95 which may be actuated over the pulse train line 71.
In the read-out of data, the transistor 95 initially is rendered conductive, as a result of which the flip-flop is set in its labile point and the digit line is thereby brought to approximately half the operating voltage (Figure 2~. Upon the selector transistor of the storage element 2 being brought into a conductive state, as previously described in connection with the circuit of Figure 1, with the aid of the current I flowing into and out of the storage element, the flip-flop circuit of the evaluator circuit is brought into a state corresponding to the stored item of data. In Figure 2, this current corresponds approximately to the current IL ~~ or the current IL "1". When the shunt transistor 95 is blocked (disconnected), as a result of the read-out current from the storage element, the evaluator flip- ~`
flop circuit will flip into the state corresponding to the stored data, which state corresponds to one of the stable points of the flip-flop circuit.
For effecting the ~ite-in of data the voltage, corresponding to the item of data to be written-in, is conducted over two transistors 42, 43, the gates of which are connected in common to the terminal 411, to the evaluator flip-flop circuit and thus, over the digit line, to the storage element. This is schematically illustra-ted in Figure 2 by the characteristic curves 83, 85, respectively. The use of a flip-flop circuit as the evaluator circuit results in the advantage of a greater speed and greater sensitivity.
It will particularly be noted, with respect to the resistance of ; the circuit to errors, that the digit line is brought approximately to the voltage which would exist at the nodal point of the storage element when it is in the labile point, which condition can be fulfilled relatively accurately ' .
1¢J 45~6 if, in the exemplary embodiment illustrated in Figure 1, the inverter stage of the evaluator circuit 1 is designed to be proportional to the controlling arm of the storage flip-flop circuit and in the circuit of Figure ~, the evaluator flip-flop is designed to be proportional to the storage flip-flop.
The term "proportional" as here utilized is to be understood to mean that the ratio of the quotients of channel width and channel length in the correspond-ing transistors is equal. In the exemplary embodiment illustrated in Figure 1, the transistors 11, 12 of the inverter stage correspond to the transistors 23, 22 respectively of the storage element and in the example of Figure 4, the transistors 91, 92, 93 and 94 of the evaluator flip-flop circuit corres-pond to the transistors 22, 23, 21 and 25 of the storage element.
In both of such cases the above mentioned condition can be accur-; ately fulfilled in the absence o deviation of the parameters of the chip.
; Having thus described our invention it will be obvious that although various minor modifications might be suggested by those versed in the art, it should be understood that we wish to embody within the scope of the patent granted hereon all such modifications as reasonably, and properly come within the scope of our contribution to the art.
Claims (8)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An evaluator circuit for reading and writing digital information out of and into a transistor storage flip-flop circuit with an individually associated selector transistor and having two operable states, corresponding to those of the storage flip-flop circuit, said evaluator circuit having an input connected to a digit line of the storage flip-flop circuit, and an output, and a shunt transistor operatively connecting the input and the out-put of the evaluator circuit, the gate of which controls the application of voltage at the output of the evaluator circuit to said digit line.
2. An evaluator circuit according to claim 1, comprising an inverter stage, and an addressing transistor operatively connected to the output of the evaluator circuit for controlling the latter.
3. An evaluator circuit according to claim 1, comprising a flip-flop circuit, one node of which is connected to the digit line and the other to the output, said shunt transistor operatively connecting the nodes thereof, and a pair of address transistors operatively connected to the respective nodes of the flip-flop circuit.
4. An arrangement as claimed in claim 1 or claim 2 wherein said flip-flop circuit is a five-transistor storage structure in the complementary-channel-MOS technique, comprising a four-transistor storage flip-flop circuit, said selector transistor operatively connecting a node of the flip-flop circuit to a digit line, a word line connecting the gate of said selector transistor for controlling the operation thereof, said flip-flop circuit being symmetrical in relation to the node to which the selector transistor is connected.
5. An arrangement as claimed in claim 3 wherein said first-mentioned flip-flop circuit is a five-transistor storage structure in the complementary-channel-MOS technique, comprising a four-transistor storage flip-flop circuit, said selector transistor operatively connecting a node of the flip-flop circuit to a digit line, a word line connecting the gate of said selec-tor transistor for controlling the operation thereof, said flip-flop circuit being symmetrical in relation to the node to which the selector transistor is connected.
6. A method for the operation of a transistor storage flip-flop element comprising a storage flip-flop circuit and a selector transistor connected to a node thereof and to a digit line having a capacitance against ground, with the selector transistor being controlled over a word line connected to its gate, which storage element is read out by means of an evaluator circuit having two operable states, corresponding to those of the storage flip-flop circuit, comprising the steps of charging the capacitance of the digit line, prior to commencement of the read-out cycle, to a predetermined voltage which corresponds approximately to the voltage which occurs across the node of the storage flip-flop circuit which is connected to the selector transistor, when the storage flip-flop circuit is in its labile point, there-after switching the selector transistor of the storage element conductive, whereby the voltage across the capacitance of the digit line is adjusted in accordance with the data stored in the storage element, to thereby set the evaluator circuit, as a result of the voltage change on the digit line, into the state corresponding to the stored data, and, during write-in, applying to the digit line a predetermined voltage corresponding to the data to be written in, as a result of which the storage flip-flop is brought into such a state when the selector transistor is conductive.
7. A method according to claim 6, wherein an inverter stage is employed as the evaluator circuit, the input being connected to the digit line, and the input and output connected to one another over a shunt trans-istor, comprising the additional steps of switching the shunt transistor conductive, prior to commencement of the read-out cycle, as a result of which the voltage at the output of the evaluator circuit is applied to the digit line, the voltage change across the digit line, following blockage of the shunt transistor, to produce at the output of the inverter stage, an electric signal which corresponds to the full voltage range of the supply voltage of the inverter stage, providing equal supply voltages across the storage element and across the inverter stage, and so dimensioning the transistors of the inverter stage of the evaluator circuit that the specified voltage is achieved when the shunt transistor is conductive.
8. A method according to claim 6, wherein a flip-flop circuit having two nodes is employed as the evaluator circuit, one node of which is con-nected to the digit line, and the two nodes of which are connected over a shunt transistor, comprising the additional steps of switching the shunt transistor conductive, prior to commencement of the read-out cycle, as a result of which the voltage at the output of the evaluator circuit is applied to the digit line, said voltage change across the digit line, corresponding to the storage content of the storage element, setting the evaluator flip-flop into a state corresponding to that of the storage flip-flop, which state corresponds to one of the two stable points of the evaluator flip-flop, and wherein for write-in, equal supply voltages are supplied across the storage element and the flip-flop of the evaluator circuit, and so dimensioning the transistors of the flip-flop of the evaulator circuit that the specified voltage is achieved when the shunt transistor is conductive.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19732317497 DE2317497C2 (en) | 1973-04-06 | 1973-04-06 | Method for operating a five-transistor memory element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1045716A true CA1045716A (en) | 1979-01-02 |
Family
ID=5877304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA196,877A Expired CA1045716A (en) | 1973-04-06 | 1974-04-04 | Method for operating transistor storage flip-flop and evaluator circuit therefor |
Country Status (12)
| Country | Link |
|---|---|
| JP (1) | JPS5760714B2 (en) |
| AT (1) | AT338018B (en) |
| BE (1) | BE813374A (en) |
| CA (1) | CA1045716A (en) |
| CH (1) | CH589344A5 (en) |
| DE (1) | DE2317497C2 (en) |
| FR (1) | FR2224836B1 (en) |
| GB (1) | GB1463621A (en) |
| IT (1) | IT1004116B (en) |
| LU (1) | LU69791A1 (en) |
| NL (1) | NL7404635A (en) |
| SE (1) | SE390354B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9135964B2 (en) | 2011-04-26 | 2015-09-15 | Soitec | Differential sense amplifier without switch transistors |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51127628A (en) * | 1975-04-28 | 1976-11-06 | Toshiba Corp | Semiconductor memory |
| JPS5345939A (en) * | 1976-10-07 | 1978-04-25 | Sharp Corp | Ram circuit |
| JPS53117340A (en) * | 1977-03-24 | 1978-10-13 | Toshiba Corp | Semiconductor memory |
| JPS54107638A (en) * | 1978-02-10 | 1979-08-23 | Sanyo Electric Co Ltd | Memory data readout circuit in semiconductor memory unit |
| US4208730A (en) * | 1978-08-07 | 1980-06-17 | Rca Corporation | Precharge circuit for memory array |
| JPS57113492A (en) * | 1981-01-07 | 1982-07-14 | Nec Corp | Memory circuit |
| JPS57173196U (en) * | 1982-03-25 | 1982-11-01 | ||
| JPS60242582A (en) * | 1984-05-16 | 1985-12-02 | Toshiba Corp | Sense amplifier of semiconductor storage device |
| JPS60242581A (en) * | 1984-05-16 | 1985-12-02 | Toshiba Corp | Sense amplifier of semiconductor storage device |
| JPH0333844U (en) * | 1989-08-09 | 1991-04-03 | ||
| FR2670061B1 (en) * | 1990-11-30 | 1996-09-20 | Bull Sa | METHOD AND DEVICE FOR TRANSFERRING DIFFERENTIAL BINARY SIGNALS AND APPLICATION TO ADDERS WITH RETENTION SELECTION. |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3644907A (en) * | 1969-12-31 | 1972-02-22 | Westinghouse Electric Corp | Complementary mosfet memory cell |
| US3600609A (en) * | 1970-02-03 | 1971-08-17 | Shell Oil Co | Igfet read amplifier for double-rail memory systems |
-
1973
- 1973-04-06 DE DE19732317497 patent/DE2317497C2/en not_active Expired
-
1974
- 1974-02-28 GB GB914474A patent/GB1463621A/en not_active Expired
- 1974-03-18 AT AT222774A patent/AT338018B/en not_active IP Right Cessation
- 1974-03-25 CH CH409174A patent/CH589344A5/xx not_active IP Right Cessation
- 1974-03-26 FR FR7410293A patent/FR2224836B1/fr not_active Expired
- 1974-03-27 SE SE7404122A patent/SE390354B/en unknown
- 1974-04-04 NL NL7404635A patent/NL7404635A/xx unknown
- 1974-04-04 CA CA196,877A patent/CA1045716A/en not_active Expired
- 1974-04-04 IT IT5007074A patent/IT1004116B/en active
- 1974-04-05 BE BE142912A patent/BE813374A/en unknown
- 1974-04-05 JP JP49038065A patent/JPS5760714B2/ja not_active Expired
- 1974-04-05 LU LU69791A patent/LU69791A1/xx unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9135964B2 (en) | 2011-04-26 | 2015-09-15 | Soitec | Differential sense amplifier without switch transistors |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5760714B2 (en) | 1982-12-21 |
| JPS49131545A (en) | 1974-12-17 |
| SE390354B (en) | 1976-12-13 |
| FR2224836A1 (en) | 1974-10-31 |
| DE2317497C2 (en) | 1975-02-13 |
| FR2224836B1 (en) | 1980-08-14 |
| CH589344A5 (en) | 1977-06-30 |
| NL7404635A (en) | 1974-10-08 |
| LU69791A1 (en) | 1974-11-21 |
| DE2317497B1 (en) | 1974-06-20 |
| BE813374A (en) | 1974-10-07 |
| GB1463621A (en) | 1977-02-02 |
| IT1004116B (en) | 1976-07-10 |
| AT338018B (en) | 1977-07-25 |
| ATA222774A (en) | 1976-11-15 |
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