GB1427259A - Testin fet circuits - Google Patents

Testin fet circuits

Info

Publication number
GB1427259A
GB1427259A GB2731273A GB2731273A GB1427259A GB 1427259 A GB1427259 A GB 1427259A GB 2731273 A GB2731273 A GB 2731273A GB 2731273 A GB2731273 A GB 2731273A GB 1427259 A GB1427259 A GB 1427259A
Authority
GB
United Kingdom
Prior art keywords
fet
bit line
voltage
gate
determining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2731273A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1427259A publication Critical patent/GB1427259A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

1427259 Memory cells INTERNATIONAL BUSINESS MACHINES CORP 8 June 1973 [3 July 1972] 27312/73 Heading H3T A method for determining electrical characteristics of a memory cell within a matrix including FETs 11, 12 having their drain electrodes connected respectively to a zero bit line 14 and a one-bit line 19 and their gate electrodes to the other of the bit lines comprises the steps of applying a constant voltage to the drain of one FET and determining its threshold voltage from a measurement of the current flow through the FET at different voltages applied to its gate. The cell may include load FETs 18, 22 whose characteristics may be determined by applying a constant voltage to the gate of associated FET 11 or 12 and changing the voltage condition at its drain by discharging the associated bit line for a first predetermined period and then determining if the charge voltage on the bit line reaches a predetermined value at the end of a second predetermined period. Initially, positive pulses are applied to terminals 31, 32 and word line 16 for setting the selected cell into its active state. For measuring the threshold voltage of FET 11, the arrangement of Fig. 3 is connected to Fig. 1. Supply 55 is set at a constant value and supply 58 is varied. By determining the difference between the voltages applied to the gate of FET 11 for two drain currents differing by a factor of four and by subtracting the lower of the two voltages from this difference, the threshold voltage is obtained. For determaning the characteristics of theload FET's 18 or 22, the arrangement of Fig. 2 is used along with that of Fig. 1. The charging time of a bit line is determined by the impedance of the associated load FET and bit line stray capacitance 29 or 30. Hence if the load is not connected to the node 17 or 21 or if it does not have the desired gain or if the leakage current from the node is excessive then the predetermined voltage will not be attained within the predetermined period.
GB2731273A 1972-07-03 1973-06-08 Testin fet circuits Expired GB1427259A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26837072A 1972-07-03 1972-07-03

Publications (1)

Publication Number Publication Date
GB1427259A true GB1427259A (en) 1976-03-10

Family

ID=23022695

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2731273A Expired GB1427259A (en) 1972-07-03 1973-06-08 Testin fet circuits

Country Status (7)

Country Link
US (1) US3795859A (en)
JP (1) JPS5338149B2 (en)
CA (1) CA996263A (en)
DE (1) DE2325871A1 (en)
FR (1) FR2237273B1 (en)
GB (1) GB1427259A (en)
IT (1) IT987133B (en)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3995215A (en) * 1974-06-26 1976-11-30 International Business Machines Corporation Test technique for semiconductor memory array
US4004222A (en) * 1974-11-20 1977-01-18 Semi Test system for semiconductor memory cell
GB2002129B (en) * 1977-08-03 1982-01-20 Sperry Rand Corp Apparatus for testing semiconductor memories
US4253059A (en) * 1979-05-14 1981-02-24 Fairchild Camera & Instrument Corp. EPROM Reliability test circuit
US4301535A (en) * 1979-07-02 1981-11-17 Mostek Corporation Programmable read only memory integrated circuit with bit-check and deprogramming modes and methods for programming and testing said circuit
WO1982000896A1 (en) * 1980-09-08 1982-03-18 Proebsting R Go/no go margin test circuit for semiconductor memory
US4409676A (en) * 1981-02-19 1983-10-11 Fairchild Camera & Instrument Corporation Method and means for diagnostic testing of CCD memories
US4519076A (en) * 1981-12-28 1985-05-21 National Semiconductor Corporation Memory core testing system
US4604531A (en) * 1983-07-25 1986-08-05 International Business Machines Corporation Imbalance circuits for DC testing
US4502140A (en) * 1983-07-25 1985-02-26 Mostek Corporation GO/NO GO margin test circuit for semiconductor memory
JPH073865B2 (en) * 1984-08-07 1995-01-18 富士通株式会社 Semiconductor integrated circuit and method of testing semiconductor integrated circuit
US4719418A (en) * 1985-02-19 1988-01-12 International Business Machines Corporation Defect leakage screen system
JP2513623B2 (en) * 1986-02-28 1996-07-03 株式会社東芝 Static memory
US4749947A (en) * 1986-03-10 1988-06-07 Cross-Check Systems, Inc. Grid-based, "cross-check" test structure for testing integrated circuits
US4739252A (en) * 1986-04-24 1988-04-19 International Business Machines Corporation Current attenuator useful in a very low leakage current measuring device
US5341092A (en) * 1986-09-19 1994-08-23 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US5223792A (en) * 1986-09-19 1993-06-29 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US4801869A (en) * 1987-04-27 1989-01-31 International Business Machines Corporation Semiconductor defect monitor for diagnosing processing-induced defects
JPH01166391A (en) * 1987-12-23 1989-06-30 Toshiba Corp Static type random access memory
US5065090A (en) * 1988-07-13 1991-11-12 Cross-Check Technology, Inc. Method for testing integrated circuits having a grid-based, "cross-check" te
US5157627A (en) * 1990-07-17 1992-10-20 Crosscheck Technology, Inc. Method and apparatus for setting desired signal level on storage element
US5179534A (en) * 1990-10-23 1993-01-12 Crosscheck Technology, Inc. Method and apparatus for setting desired logic state at internal point of a select storage element
US5222066A (en) * 1990-12-26 1993-06-22 Motorola, Inc. Modular self-test for embedded SRAMS
US5206862A (en) * 1991-03-08 1993-04-27 Crosscheck Technology, Inc. Method and apparatus for locally deriving test signals from previous response signals
US5230001A (en) * 1991-03-08 1993-07-20 Crosscheck Technology, Inc. Method for testing a sequential circuit by splicing test vectors into sequential test pattern
US5166608A (en) * 1991-11-07 1992-11-24 Advanced Micro Devices, Inc. Arrangement for high speed testing of field-effect transistors and memory cells employing the same
US6000843A (en) * 1992-07-03 1999-12-14 Nippon Steel Corporation Electrically alterable nonvolatile semiconductor memory
US5325054A (en) * 1992-07-07 1994-06-28 Texas Instruments Incorporated Method and system for screening reliability of semiconductor circuits
JP2822951B2 (en) * 1995-08-28 1998-11-11 日本電気株式会社 Evaluation element of insulated gate field effect transistor, evaluation circuit and evaluation method using the same
US6330697B1 (en) * 1999-04-20 2001-12-11 International Business Machines Corporation Apparatus and method for performing a defect leakage screen test for memory devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3490007A (en) * 1965-12-24 1970-01-13 Nippon Electric Co Associative memory elements using field-effect transistors
US3713114A (en) * 1969-12-18 1973-01-23 Ibm Data regeneration scheme for stored charge storage cell
US3610967A (en) * 1970-02-27 1971-10-05 Ibm Integrated memory cell circuit
US3727196A (en) * 1971-11-29 1973-04-10 Mostek Corp Dynamic random access memory
US3714638A (en) * 1972-03-24 1973-01-30 Rca Corp Circuit for improving operation of semiconductor memory

Also Published As

Publication number Publication date
JPS4959542A (en) 1974-06-10
FR2237273A1 (en) 1975-02-07
DE2325871A1 (en) 1974-01-17
JPS5338149B2 (en) 1978-10-13
CA996263A (en) 1976-08-31
US3795859A (en) 1974-03-05
IT987133B (en) 1975-02-20
FR2237273B1 (en) 1976-09-24

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee