JP2513623B2 - Static memory - Google Patents

Description

The present invention relates to a semiconductor memory, and more particularly to a bit line potential measuring / setting circuit in a static memory.

(Prior Art) FIG. 4 schematically shows a memory cell array and its peripheral circuits in a conventional static memory. In the memory cell array, a plurality of static type memory cells 1 ... Are arranged in a matrix, and one memory cell 1 is arbitrarily selected by a row selection signal and a column selection signal. 2 of each memory cell 1 ...
One data input / output node has a pair of bit lines BL, ▲ ▼
, And a precharge circuit 2, a sense amplifier and a write circuit 3 are connected to each bit line BL, ▲ ▼ pair. A data input line 4 for transmitting write data to the memory cells 1 ... And a data output line 5 for transmitting read data from the memory cells 1 ... Are connected to the sense amplifier and write circuit 3.

The operation of the static memory is well known, and its outline is as follows. At the time of reading, the potentials of the bit lines BL, ▲ ▼ are equally charged to near the memory power supply voltage by the precharge circuit 2, and an arbitrary memory cell is selected and at the same time a pair of bit lines BL, ▲ connected to it. A potential difference is added to ▼, and this potential difference is sense-amplified by a sense amplifier, and this amplified output is output to the outside. At the time of writing, the write circuit 3 sets in advance potentials contradictory to the bit lines BL and ▲ ▼, so that an arbitrary memory cell is selected and at the same time, the potential of the pair of bit lines BL and ▲ ▼ connected to it causes the memory cell The data is written in.

By the way, in the above-mentioned conventional static type memory, since the potential difference generated between the pair of bit lines BL, ▲ ▼ connected to the selected memory cell at the time of reading is small, an error occurs in the sense operation by the sense amplifier and the read operation is performed. There may be defects. Particularly, with the recent miniaturization of circuit elements, the performance of the MOS transistor in the memory cell deteriorates, and the potential difference becomes small, so that the read failure tends to occur. In addition, with the miniaturization of the above circuit elements, a slight variation in the manufacturing process has a great influence on the operational margin of the circuit.
It is also conceivable that malfunction of the circuit is likely to occur. Therefore, when trying to evaluate the memory characteristics, it is possible to make some predictions by using various test methods in the conventional static memory, but it is inevitable to confirm the circuit operation (especially for bit It is not possible to confirm the line potential), and a large amount of time is required for the above evaluation. Moreover, the conventional static type memory cannot forcibly set the bit line potential from the outside of the memory during the failure analysis of the memory characteristics at the development stage.

(Problems to be Solved by the Invention) The present invention has been made to solve the above-described problem that the bit line potential cannot be measured or forcibly set. It is an object of the present invention to provide a static memory which can be forcedly set from the outside and which can facilitate the evaluation of memory characteristics or the failure analysis and the time required therefor.

[Structure of Invention]

(Means for Solving Problems) In the static memory of the present invention, one end of each MOS switch is connected to each bit line of the memory cell array,
All or part of these MOS switches corresponding to at least one column can be switch-controlled to the same state on the basis of a control signal from the outside of the memory, and the other end of the MOS switch can be controlled to have a potential outside the memory. It is characterized in that the potential can be forcibly set from the outside of the measurement or the memory.

(Function) The MOS switch is controlled to the ON state during memory characteristic evaluation or failure analysis, the bit line potential is read out during evaluation, and a prescribed potential is forced from the outside to the bit line during failure analysis. Is applied. Further, during the normal operation of the memory, the MOS switch is controlled to be in the off state, so that the memory operation is not affected.

Therefore, it becomes possible to easily evaluate the memory characteristic or analyze the failure, and the time required therefor can be shortened. Moreover, the bit line potential measurement as described above
Only a few additional circuits are required for the setting.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

Figure 1 shows a part of static memory,
A bit line potential measuring / setting circuit 10 is added to the conventional static memory described with reference to FIG. 4, and the other parts are the same as those in FIG. And its description is omitted.

In the above memory, the bit line BL ₁ , ▲ ▼,
…, BL _n , and ▲ ▼ each have a MOS switch (for example, N-channel enhancement type MOS transistor).
One end of each of T ₁ , ..., T _n ,) is connected.
Then, of the MOS switches, the bit line BL ₁ on the positive phase side,
... The other ends of the MOS switches connected to BL _n are commonly connected to the first signal line 11, and the remaining bit lines on the opposite phase side ▲
The other ends of the MOS switches connected to ▼, ..., ▲ ▼ are commonly connected to the second signal line 12. Further, the gates of the MOS switches are commonly connected to the switch control signal line 13.

In the memory, each of the MOS switches can be turned on or off by a switch control signal applied to the switch control signal line 13.

Therefore, when the memory characteristics are evaluated, by setting each of the MOS switches to the ON state, the bit lines BL ₁ , ..., BL _n and ▲ ▼, ..., ▲ at that time are set.
The potential of ▼ is MOS transistor T ₁ ,…, T _n and ▲
The signals are output to the first signal line 11 and the second signal line 12 through ▼, ..., ▲ ▼, and the output potential of the bit line is led to the outside of the memory either directly or through another circuit element to change the bit line potential. It becomes possible to measure. In this case, the positive signal side bit line BL is used as the first signal line 11.
The balanced value of each potential of ₁ , ... BL _n is output, and the bit line on the opposite phase side ▲ ▼,…, ▲ is output to the second signal line 12.
The balanced value of each potential of ▼ is output. Similarly,
Even when analyzing memory characteristic defects, by setting each MOS switch to the ON state, the first
Of the bit line BL on the positive phase side through the MOS transistors T ₁ , ..., T _n by forcibly applying a predetermined potential to the signal line 11 and the second signal line 12 directly or through other circuit elements. ₁ ,…, BL _n Also MOS transistor ▲
Bit line on the opposite phase side through ▼,…, ▲ ▼
It becomes possible to set each potential of ▼,…, ▲ ▼.

By setting each MOS switch to the off state, it is possible to perform the normal operation of the memory as in the conventional case.

By the way, in the above embodiment, the potential measurement or the potential setting can be performed commonly for all the bit line pairs, but the present invention is not limited to this, and one bit line pair is arbitrarily selected and set to the ON state. Thus, the path between the bit line pair and the first and second signal lines 11 and 12 is switched in each column unit of the memory cell array so that the potential of the one bit line pair can be measured or set. It may be modified to be controllable.

To this end, as shown in FIG. 2, a pair of bit lines BL, ▲ ▼ and the first and second signal lines 1 in each column are provided.
A pair of MOs connected to 1 and 12 respectively
The S switches T _i and ▲ ▼ are input to the 2-input AND circuit 21 by inputting the signal of the switch control signal line 13 commonly used in each column and the column selection signal CD for selecting the column of the memory cell array. It may be changed so as to control the switch by the output of the logical product. Alternatively, the third
As shown in the figure, a pair of bit lines BL in each column,
Two MOS switches T _i and T _i ′ and ▲ ▼ and ▲ ▼ connected in series are connected between ▲ ▼ and the first and second signal lines 11 and 12, and one of the MOS switches is connected. switch
T _i , ▲ ▼ (or T _i ′, ▲ ▼) is switch-controlled by the switch control signal of the switch control signal line 13, and the remaining MOS switches T _i ′, ▲ ▼ (or T _i ,
▲ ▼) may be changed so as to be switch-controlled by the column selection signal CD of the column selection signal line. The second
In FIG. 3 and FIG. 3, 1 is a memory cell, and 6 is a row selection signal line.

Although the N-channel MOS transistors are used as the MOS switches in each of the above embodiments, the present invention is not limited to this, and P-channel MOS transistors and other MOS switch circuits may be used.

〔The invention's effect〕

As described above, according to the static memory of the present invention, it is possible to measure the bit line potential or forcibly set it from the outside, so that the evaluation of memory characteristics or failure analysis can be performed easily and in a short time. it can. Moreover,
The circuit configuration necessary to enable the measurement of the bit line potential or the forced operation from the outside is simple.

[Brief description of drawings]

FIG. 1 is a circuit diagram schematically showing a part of an embodiment of a static memory of the present invention, and FIGS. 2 and 3 are a part of individual columns in another embodiment respectively. FIG. 4 is a circuit diagram schematically showing a part of a conventional static type memory. 1 ... Static type memory cell, 10 ... Circuit for measuring / setting bit line potential, 11 ... First signal line, 12 ... Second signal line,
13 ... Switch control signal line, 21 ... AND circuit, T ₁ , ▲
▼,… ▲ ▼, ▲ ▼, T _i , ▲ ▼, T _i ′, ▲
▼… MOS transistor, BL ₁ , ▲ ▼,…, B
L _n , ▲ ▼, BL, ▲ ▼ ... Bit line, CD ... Column selection signal.

Claims (1)

(57) [Claims] 1. A memory cell array having a plurality of columns, a positive phase side bit line group and a negative phase side bit line group formed in each column of the memory cell array, and one end formed in each column. A first MOS transistor group directly connected to the positive phase side bit line group and a second MOS transistor group formed in each column and having one end directly connected to the negative phase side bit line group and formed in each column A switch control signal for turning on the first and second MOS transistor groups and a column selection signal for performing column selection of the memory cell array are input, and output signals are output to gates of the first and second MOS transistor groups. , A first signal line commonly connected to the other end of the first MOS transistor group in all columns, and the second MOS transistor in all columns. A second signal line commonly connected to the other end of the memory group, and a read / write circuit for reading / writing data from / to each memory cell of the memory cell array. In the logic circuit group, based on the switch control signal and the column selection signal,
The logic is such that the first and second MOS transistors in the selected column are turned on and the first and second MOS transistors in the unselected column are turned off, and the first signal line is connected to the selected column. The potential of the bit line on the positive phase side is output to the outside of the memory, the second signal line outputs the potential of the bit line on the opposite phase side of the selected column to the outside of the memory, and the read / write circuit includes A static memory, which does not operate when evaluating the characteristics of the memory, but operates during normal operation.