JPS57113492A - Memory circuit - Google Patents
Memory circuitInfo
- Publication number
- JPS57113492A JPS57113492A JP100181A JP100181A JPS57113492A JP S57113492 A JPS57113492 A JP S57113492A JP 100181 A JP100181 A JP 100181A JP 100181 A JP100181 A JP 100181A JP S57113492 A JPS57113492 A JP S57113492A
- Authority
- JP
- Japan
- Prior art keywords
- level
- signal
- phis
- point
- becomes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/32—Non-reciprocal transmission devices
- H01P1/36—Isolators
Landscapes
- Read Only Memory (AREA)
Abstract
PURPOSE:To execute an operation at a high speed, and also to reduce the power consumption, by storing a charging voltage level in the capacity, making this charging level a reference, to execute a differential amplification. CONSTITUTION:Digit lines Dj, Dj+1 are charged by transistors (TR) Tpj, Tpj+1 when this gate input signal -phis is in an H level, and an input point A of a sense-up part 2 after a Y-selector is also charged through a TR T2. When the signal -phis becomes a low level after charging, subsequently, a comparing input level point B is cut off by a TR T1 of a gate signal -phis', and charge of a floating capacity CF is held. Decoder outputs Xi, Yj are selected, a signal phi becomes a high level, a low threshold level TR conducts, a resistance TR T4 conducts, and if there is a TR in a selected cell, the line Dj is discharged. Accordingly, the point A is connected to the line Dj through a TR Tsj, and becomes an almost same waveform. From a rise time of a signal phis to a fall time of -phis2, the signal is outputted from a sense amplifier 1 for amplifying a level difference between the point A and B, through an output buffer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP100181A JPS57113492A (en) | 1981-01-07 | 1981-01-07 | Memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP100181A JPS57113492A (en) | 1981-01-07 | 1981-01-07 | Memory circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57113492A true JPS57113492A (en) | 1982-07-14 |
JPS627640B2 JPS627640B2 (en) | 1987-02-18 |
Family
ID=11489339
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP100181A Granted JPS57113492A (en) | 1981-01-07 | 1981-01-07 | Memory circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57113492A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59151392A (en) * | 1983-02-16 | 1984-08-29 | Sharp Corp | Semiconductor read only memory circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49131545A (en) * | 1973-04-06 | 1974-12-17 |
-
1981
- 1981-01-07 JP JP100181A patent/JPS57113492A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49131545A (en) * | 1973-04-06 | 1974-12-17 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59151392A (en) * | 1983-02-16 | 1984-08-29 | Sharp Corp | Semiconductor read only memory circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS627640B2 (en) | 1987-02-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB1525810A (en) | Clock generator and delay stage | |
JPS54139344A (en) | Clock-system static memory | |
ES439584A1 (en) | Differential charge transfer sense amplifier | |
JPS53134337A (en) | Sense circuit | |
JPS5758297A (en) | Semiconductor storage device | |
JPS56129570A (en) | Booster circuit | |
JPS57141097A (en) | Storage circuit | |
JPS56130885A (en) | Address buffer circuit | |
JPS5755592A (en) | Memory device | |
GB1524665A (en) | Memeory circuit arrangement utilizing one-transistor-per-bit memory cells | |
JPS5648715A (en) | Delay signal generating circuit | |
JPS57103195A (en) | Semiconductor storage device | |
EP0910095A3 (en) | Low voltage sample and hold circuits | |
ES470267A1 (en) | Capacitor memory with an amplified cell signal | |
GB1459951A (en) | Shift registers | |
JPS5693178A (en) | Semiconductor memory device | |
JPS5538611A (en) | Memory circuit | |
JPS57113492A (en) | Memory circuit | |
JPS55113188A (en) | Mos memory driver circuit | |
JPS57103426A (en) | Pulse generating circuit | |
JPS56107387A (en) | Semiconductor storage device | |
JPS5641593A (en) | Semiconductor memory unit | |
JPS54107638A (en) | Memory data readout circuit in semiconductor memory unit | |
JPS54100233A (en) | Integrated memory | |
JPS57195387A (en) | Data lien precharging system of memory integrated circuit |