CA1009769A - Semiconductor etchant having uniform etch rate - Google Patents

Semiconductor etchant having uniform etch rate

Info

Publication number
CA1009769A
CA1009769A CA210,313A CA210313A CA1009769A CA 1009769 A CA1009769 A CA 1009769A CA 210313 A CA210313 A CA 210313A CA 1009769 A CA1009769 A CA 1009769A
Authority
CA
Canada
Prior art keywords
etch rate
uniform etch
semiconductor etchant
etchant
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA210,313A
Other languages
English (en)
Other versions
CA210313S (en
Inventor
Hendrik A.D. Claes
Wolter G. Gelling
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of CA1009769A publication Critical patent/CA1009769A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • ing And Chemical Polishing (AREA)
  • Surface Treatment Of Glass (AREA)
CA210,313A 1973-10-03 1974-09-30 Semiconductor etchant having uniform etch rate Expired CA1009769A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7313572A NL7313572A (nl) 1973-10-03 1973-10-03 Werkwijze voor het etsen van silicium- of ger- mplakken en halfgeleiderinrichtingen ver- igd met toepassing van deze werkwijze.

Publications (1)

Publication Number Publication Date
CA1009769A true CA1009769A (en) 1977-05-03

Family

ID=19819730

Family Applications (1)

Application Number Title Priority Date Filing Date
CA210,313A Expired CA1009769A (en) 1973-10-03 1974-09-30 Semiconductor etchant having uniform etch rate

Country Status (8)

Country Link
US (1) US3966517A (de)
JP (1) JPS5062775A (de)
CA (1) CA1009769A (de)
DE (1) DE2445882C2 (de)
FR (1) FR2246979B1 (de)
GB (1) GB1469013A (de)
IT (1) IT1022491B (de)
NL (1) NL7313572A (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4137123A (en) * 1975-12-31 1979-01-30 Motorola, Inc. Texture etching of silicon: method
US4078945A (en) * 1976-05-03 1978-03-14 Mobil Tyco Solar Energy Corporation Anti-reflective coating for silicon solar cells
US4092211A (en) * 1976-11-18 1978-05-30 Northern Telecom Limited Control of etch rate of silicon dioxide in boiling phosphoric acid
US4615762A (en) * 1985-04-30 1986-10-07 Rca Corporation Method for thinning silicon
US5348617A (en) * 1991-12-23 1994-09-20 Iowa State University Research Foundation, Inc. Selective etching process
KR970008354B1 (ko) * 1994-01-12 1997-05-23 엘지반도체 주식회사 선택적 식각방법
US5439553A (en) 1994-03-30 1995-08-08 Penn State Research Foundation Controlled etching of oxides via gas phase reactions
EP0758797A1 (de) * 1995-08-11 1997-02-19 AT&T Corp. Ätzverfahren für Siliziumnitrid
US5843322A (en) * 1996-12-23 1998-12-01 Memc Electronic Materials, Inc. Process for etching N, P, N+ and P+ type slugs and wafers
DE19721493A1 (de) * 1997-05-22 1998-11-26 Wacker Siltronic Halbleitermat Verfahren zum Ätzen von Halbleiterscheiben
TW511180B (en) * 2000-07-31 2002-11-21 Mitsubishi Chem Corp Mixed acid solution in etching process, process for producing the same, etching process using the same and process for producing semiconductor device
KR100652788B1 (ko) * 2004-10-26 2006-12-01 다이닛뽕스크린 세이조오 가부시키가이샤 웨이퍼 처리장치 및 웨이퍼 처리방법
EP1926132A1 (de) * 2006-11-23 2008-05-28 S.O.I.Tec Silicon on Insulator Technologies Chromfreie Ätzlösung für Si-Substrate und SiGe-substrate, Verfahren zum Präparieren von Defekten diese Ätzlösung verwendend und Verfahren zum Behnadeln von Si-Substraten und SiGe-Substraten
DE102014013591A1 (de) 2014-09-13 2016-03-17 Jörg Acker Verfahren zur Herstellung von Siliciumoberflächen mit niedriger Reflektivität
CN114316990B (zh) * 2021-12-09 2023-04-07 湖北兴福电子材料股份有限公司 一种高蚀刻锥角的锗蚀刻液

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3762973A (en) * 1969-04-01 1973-10-02 Gen Electric Method of etch subdividing semiconductor wafers
US3844859A (en) * 1969-12-16 1974-10-29 Boeing Co Titanium chemical milling etchant
US3677848A (en) * 1970-07-15 1972-07-18 Rca Corp Method and material for etching semiconductor bodies
US3716425A (en) * 1970-08-24 1973-02-13 Motorola Inc Method of making semiconductor devices through overlapping diffusions

Also Published As

Publication number Publication date
US3966517A (en) 1976-06-29
DE2445882A1 (de) 1975-04-17
IT1022491B (it) 1978-03-20
NL7313572A (nl) 1975-04-07
JPS5062775A (de) 1975-05-28
DE2445882C2 (de) 1983-12-29
GB1469013A (en) 1977-03-30
FR2246979B1 (de) 1978-06-16
FR2246979A1 (de) 1975-05-02

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