BRPI0716969A8 - Sistema de processamento gráfico acelerado - Google Patents

Sistema de processamento gráfico acelerado

Info

Publication number
BRPI0716969A8
BRPI0716969A8 BRPI0716969A BRPI0716969A BRPI0716969A8 BR PI0716969 A8 BRPI0716969 A8 BR PI0716969A8 BR PI0716969 A BRPI0716969 A BR PI0716969A BR PI0716969 A BRPI0716969 A BR PI0716969A BR PI0716969 A8 BRPI0716969 A8 BR PI0716969A8
Authority
BR
Brazil
Prior art keywords
video
processing
time
graphics
period
Prior art date
Application number
BRPI0716969A
Other languages
English (en)
Inventor
Gonzalez Nelson
Organvidez Humberto
H Organvidez Juan
Original Assignee
Alienware Labs Corp
Dell Marketing L P
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alienware Labs Corp, Dell Marketing L P filed Critical Alienware Labs Corp
Publication of BRPI0716969A2 publication Critical patent/BRPI0716969A2/pt
Publication of BRPI0716969A8 publication Critical patent/BRPI0716969A8/pt
Publication of BRPI0716969B1 publication Critical patent/BRPI0716969B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/42—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/12—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/123—Frame memory handling using interleaving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Computing Systems (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)

Abstract

SISTEMA DE PROCESSAMENTO GRÁFICO ACELERADO, MÉTODO PARA EQUILIBRAR CARGAS PARA UMA PLURALIDADE DE PROCESSADORES GRÁFICOS CONFIGURADOS PARA OPERAR EM PARALELO E SISTEMA DE PROCESSAMENTO GRÁFICO Um subsistema de processamento gráfico acelerado combina a potência de processamento de múltiplas unidades de processamento gráfico (GPUs) ou placas de vídeo. O processamento de vídeo através de múltiplas placas de vídeo é organizado por divisão de tempo tal que cada placa de vídeo é responsável pelo processamento de dados de vídeo durante um período de tempo diferente. Por exemplo, duas placas de vídeo podem ser alternadas, com a primeira placa de vídeo controlando uma tela por um certo período de tempo e a segunda placa de vídeo assumindo sequencialmente as responsabilidades de processamento de vídeo por um período subseqüente. Desta forma, à medida que uma placa de vídeo está gerenciando a exibição em um período de tempo, a segunda placa de vídeo está processando os dados de vídeo pelo próximo período de tempo, desse modo permitindo um processamento extensivo dos dados de vídeo antes do início do próximo período de tempo. A presente invenção pode adicionalmente incorporar o equilíbrio de cargas tal que a duração dos períodos de tempo de processamento para cada placa de vídeo seja dinamicamente modificada para maximizar o processamento de vídeo composto.
BRPI0716969A 2006-09-18 2007-09-18 sistema de processamento gráfico acelerado BRPI0716969B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/522,525 US20080211816A1 (en) 2003-07-15 2006-09-18 Multiple parallel processor computer graphics system
US11/522.525 2006-09-18
PCT/US2007/020125 WO2008036231A2 (en) 2006-09-18 2007-09-18 Multiple parallel processor computer graphics system

Publications (3)

Publication Number Publication Date
BRPI0716969A2 BRPI0716969A2 (pt) 2013-11-05
BRPI0716969A8 true BRPI0716969A8 (pt) 2017-08-15
BRPI0716969B1 BRPI0716969B1 (pt) 2018-12-18

Family

ID=39201050

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0716969A BRPI0716969B1 (pt) 2006-09-18 2007-09-18 sistema de processamento gráfico acelerado

Country Status (6)

Country Link
US (1) US20080211816A1 (pt)
CN (1) CN101548277B (pt)
BR (1) BRPI0716969B1 (pt)
DE (1) DE112007002200T5 (pt)
GB (1) GB2455249B (pt)
WO (1) WO2008036231A2 (pt)

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Also Published As

Publication number Publication date
GB0904650D0 (en) 2009-04-29
GB2455249B (en) 2011-09-21
BRPI0716969B1 (pt) 2018-12-18
CN101548277B (zh) 2015-11-25
US20080211816A1 (en) 2008-09-04
DE112007002200T5 (de) 2009-07-23
WO2008036231A2 (en) 2008-03-27
BRPI0716969A2 (pt) 2013-11-05
GB2455249A (en) 2009-06-10
CN101548277A (zh) 2009-09-30
WO2008036231A3 (en) 2008-11-27

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