BR112018005874A2 - gerenciamento de recurso proativo para sistemas paralelos de processamento de roubo de trabalho - Google Patents

gerenciamento de recurso proativo para sistemas paralelos de processamento de roubo de trabalho

Info

Publication number
BR112018005874A2
BR112018005874A2 BR112018005874A BR112018005874A BR112018005874A2 BR 112018005874 A2 BR112018005874 A2 BR 112018005874A2 BR 112018005874 A BR112018005874 A BR 112018005874A BR 112018005874 A BR112018005874 A BR 112018005874A BR 112018005874 A2 BR112018005874 A2 BR 112018005874A2
Authority
BR
Brazil
Prior art keywords
processor
work
ready
victim
work items
Prior art date
Application number
BR112018005874A
Other languages
English (en)
Inventor
Suárez Gracia Dario
Zhao Han
Kumar Tushar
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018005874A2 publication Critical patent/BR112018005874A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5083—Techniques for rebalancing the load in a distributed system
    • G06F9/5088—Techniques for rebalancing the load in a distributed system involving task migration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4893—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues taking into account power or heat criteria
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4818—Priority circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5083—Techniques for rebalancing the load in a distributed system
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Hardware Redundancy (AREA)

Abstract

trata-se de diversas modalidades para balancear de modo proativo cargas de trabalho entre uma pluralidade de unidades de processamento de um dispositivo de computação com múltiplos processadores criando-se determinações de roubo de trabalho com base em dados de estado operante. um método da modalidade inclui obter dados de características estáticas associados a cada um dentre um processador-vítima e um ou mais dentre uma pluralidade de unidades de processamento que estão prontas para roubar itens de trabalho do processador-vítima (processadores prontos para o trabalho), obter dados de características dinâmicas para cada um dos processadores, calcular valores de prioridade para cada um dos processadores com base nos dados obtidos, e transferir inúmeros itens de trabalho atribuídos ao processador-vítima para um processador vencedor pronto para o trabalho com base nos valores de prioridade calculados. em algumas modalidades, o método pode incluir adquirir controle sobre uma trava probabilística para uma estrutura de dados compartilhada e atualizar a estrutura de dados compartilhada para indicar o número de itens de trabalho transferidos para o processador vencedor pronto para o trabalho.
BR112018005874A 2015-09-23 2016-08-26 gerenciamento de recurso proativo para sistemas paralelos de processamento de roubo de trabalho BR112018005874A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/862,373 US10360063B2 (en) 2015-09-23 2015-09-23 Proactive resource management for parallel work-stealing processing systems
PCT/US2016/048989 WO2017053004A1 (en) 2015-09-23 2016-08-26 Proactive resource management for parallel work-stealing processing systems

Publications (1)

Publication Number Publication Date
BR112018005874A2 true BR112018005874A2 (pt) 2018-10-16

Family

ID=56853894

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018005874A BR112018005874A2 (pt) 2015-09-23 2016-08-26 gerenciamento de recurso proativo para sistemas paralelos de processamento de roubo de trabalho

Country Status (7)

Country Link
US (1) US10360063B2 (pt)
EP (1) EP3353654A1 (pt)
JP (1) JP2018531450A (pt)
KR (1) KR20180057684A (pt)
CN (1) CN108139939A (pt)
BR (1) BR112018005874A2 (pt)
WO (1) WO2017053004A1 (pt)

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US11321144B2 (en) * 2019-06-29 2022-05-03 Intel Corporation Method and apparatus for efficiently managing offload work between processing units
US10929129B2 (en) 2019-06-29 2021-02-23 Intel Corporation Apparatus and method for modifying addresses, data, or program code associated with offloaded instructions
US10983796B2 (en) 2019-06-29 2021-04-20 Intel Corporation Core-to-core end “offload” instruction(s)
US11182208B2 (en) 2019-06-29 2021-11-23 Intel Corporation Core-to-core start “offload” instruction(s)
US11372711B2 (en) 2019-06-29 2022-06-28 Intel Corporation Apparatus and method for fault handling of an offload transaction
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Also Published As

Publication number Publication date
US10360063B2 (en) 2019-07-23
US20170083364A1 (en) 2017-03-23
JP2018531450A (ja) 2018-10-25
EP3353654A1 (en) 2018-08-01
CN108139939A (zh) 2018-06-08
KR20180057684A (ko) 2018-05-30
WO2017053004A1 (en) 2017-03-30

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal acc. article 33 of ipl - extension of time limit for request of examination expired