BR9713948A - Processo para converção de um sinal de entrada digital de um predeterminado número inteiro, n, de bits b (i) em sinal de saìda analógico, conversor digital-para-analógico, e, estágio direcionado para um conversor digital-para-analógico - Google Patents
Processo para converção de um sinal de entrada digital de um predeterminado número inteiro, n, de bits b (i) em sinal de saìda analógico, conversor digital-para-analógico, e, estágio direcionado para um conversor digital-para-analógicoInfo
- Publication number
- BR9713948A BR9713948A BR9713948A BR9713948A BR9713948A BR 9713948 A BR9713948 A BR 9713948A BR 9713948 A BR9713948 A BR 9713948A BR 9713948 A BR9713948 A BR 9713948A BR 9713948 A BR9713948 A BR 9713948A
- Authority
- BR
- Brazil
- Prior art keywords
- digital
- analog converter
- algorithm
- analog
- gray
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/667—Recirculation type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
- H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
- H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/40—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
- H03M1/403—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type using switched capacitors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/72—Sequential conversion in series-connected stages
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
D/A de um sinal de entrada digital codificado de Gray é realizada de acordo com um inventivo recursivo algoritmo de conversão de código-para-analógico de Gray. De acordo com o recursivo algoritmo, os bits de código de Gray da entrada digital são sucessivamente aplicados nas recursões do algoritmo, ualização de um sinal intermediário. Em cada recursão, o sinal intermediário é seletivamente invertido na dependência do particular bit de código de Gr do sinal intermediário é uma inerente propriedade do algoritmo de código-para-analógico de Gray, e é um fator chave para reduzir a acumulação de erros em uma conversão D/A. Em uma arquitetura de conversor D/A baseada no algoritmo, a acumulação de erros de desvioserá baixa,. Além disso, o fato que a inversão de sinal é controlada digitalmente permite implementações de alta precisão, ademais aperfeiçoando o desempenho do conversor D/A.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9604617A SE9604617L (sv) | 1996-12-16 | 1996-12-16 | Cyklisk analog-digitalomvandling |
SE9604616A SE9604616L (sv) | 1996-12-16 | 1996-12-16 | Analog-digitalomvandling av pipelinetyp |
SE9701812A SE9701812L (sv) | 1996-12-16 | 1997-05-15 | Omvandlare |
PCT/SE1997/002039 WO1998027656A2 (en) | 1996-12-16 | 1997-12-05 | Digital-to-analog conversion |
Publications (1)
Publication Number | Publication Date |
---|---|
BR9713948A true BR9713948A (pt) | 2000-03-21 |
Family
ID=27355850
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR9713948A BR9713948A (pt) | 1996-12-16 | 1997-12-05 | Processo para converção de um sinal de entrada digital de um predeterminado número inteiro, n, de bits b (i) em sinal de saìda analógico, conversor digital-para-analógico, e, estágio direcionado para um conversor digital-para-analógico |
Country Status (11)
Country | Link |
---|---|
US (1) | US6078276A (pt) |
EP (1) | EP1008236B1 (pt) |
JP (1) | JP3844510B2 (pt) |
CN (1) | CN1169301C (pt) |
AU (1) | AU723554B2 (pt) |
BR (1) | BR9713948A (pt) |
CA (1) | CA2275613A1 (pt) |
DE (1) | DE69727981T2 (pt) |
SE (1) | SE9701812L (pt) |
TW (1) | TW385594B (pt) |
WO (1) | WO1998027656A2 (pt) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6870495B1 (en) * | 2004-02-18 | 2005-03-22 | Micron Technology, Inc. | Double throughput analog to digital converter |
CN100384088C (zh) * | 2004-12-21 | 2008-04-23 | 北京中星微电子有限公司 | 一种数模信号转换的方法及数模信号转换装置 |
JP2006243232A (ja) * | 2005-03-02 | 2006-09-14 | Seiko Epson Corp | 基準電圧発生回路、表示ドライバ、電気光学装置及び電子機器 |
JP4810840B2 (ja) * | 2005-03-02 | 2011-11-09 | セイコーエプソン株式会社 | 基準電圧発生回路、表示ドライバ、電気光学装置及び電子機器 |
US7746261B2 (en) * | 2007-08-01 | 2010-06-29 | Denso Corporation | Variable gain amplifier and D/A converter |
US7948410B2 (en) * | 2009-07-20 | 2011-05-24 | Texas Instruments Incorporated | Multibit recyclic pipelined ADC architecture |
JP6762733B2 (ja) * | 2016-03-01 | 2020-09-30 | 東芝情報システム株式会社 | D/a変換装置及びd/a変換方法 |
US11536818B2 (en) | 2019-06-25 | 2022-12-27 | Bfly Operations, Inc. | Methods and apparatuses for processing ultrasound signals |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3701152A (en) * | 1970-07-20 | 1972-10-24 | Us Navy | Bipolar sample and hold circuit |
DE3400061A1 (de) * | 1984-01-03 | 1985-07-25 | Günter Dipl.-Phys. 3303 Vechelde Kramer | Digital-analog-wandler |
DE3413456A1 (de) * | 1984-04-10 | 1985-10-17 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Digital/analog-umsetzer |
US4596979A (en) * | 1984-05-17 | 1986-06-24 | Norwood Sisson | Fast response digital-to-analog converter |
US4591826A (en) * | 1984-06-14 | 1986-05-27 | Harris Corporation | Gray code DAC ladder |
US5180932A (en) * | 1990-03-15 | 1993-01-19 | Bengel David W | Current mode multiplexed sample and hold circuit |
US5404143A (en) * | 1991-06-12 | 1995-04-04 | Intellectual Property Development Associates Of Connecticut, Inc. | Network swappers and circuits constructed from same |
US5424740A (en) * | 1993-08-11 | 1995-06-13 | Holtek Microelectronics Inc. | Digital-to-analog converter with a Johnson code generator |
US5798747A (en) * | 1995-11-17 | 1998-08-25 | National Semiconductor Corporation | Methods and apparatuses for high-speed video sample and hold amplification for analog flat panel display |
KR0170720B1 (ko) * | 1995-12-29 | 1999-03-30 | 김광호 | 디지탈/아날로그 변환기 인터페이스 장치 |
-
1997
- 1997-05-15 SE SE9701812A patent/SE9701812L/ not_active Application Discontinuation
- 1997-12-05 CN CNB971806519A patent/CN1169301C/zh not_active Expired - Fee Related
- 1997-12-05 JP JP52759798A patent/JP3844510B2/ja not_active Expired - Fee Related
- 1997-12-05 AU AU54228/98A patent/AU723554B2/en not_active Ceased
- 1997-12-05 CA CA002275613A patent/CA2275613A1/en not_active Abandoned
- 1997-12-05 EP EP97948089A patent/EP1008236B1/en not_active Expired - Lifetime
- 1997-12-05 DE DE69727981T patent/DE69727981T2/de not_active Expired - Lifetime
- 1997-12-05 WO PCT/SE1997/002039 patent/WO1998027656A2/en active IP Right Grant
- 1997-12-05 BR BR9713948A patent/BR9713948A/pt not_active IP Right Cessation
- 1997-12-15 TW TW086118909A patent/TW385594B/zh not_active IP Right Cessation
- 1997-12-15 US US08/990,940 patent/US6078276A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
SE9701812L (sv) | 1998-06-17 |
AU723554B2 (en) | 2000-08-31 |
JP2001506440A (ja) | 2001-05-15 |
SE9701812D0 (sv) | 1997-05-15 |
US6078276A (en) | 2000-06-20 |
CN1169301C (zh) | 2004-09-29 |
WO1998027656A3 (en) | 1998-08-06 |
JP3844510B2 (ja) | 2006-11-15 |
AU5422898A (en) | 1998-07-15 |
DE69727981D1 (de) | 2004-04-08 |
EP1008236B1 (en) | 2004-03-03 |
DE69727981T2 (de) | 2005-01-05 |
TW385594B (en) | 2000-03-21 |
CA2275613A1 (en) | 1998-06-25 |
EP1008236A2 (en) | 2000-06-14 |
CN1242116A (zh) | 2000-01-19 |
WO1998027656A2 (en) | 1998-06-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4703308A (en) | Apparatus and methods for digital-to-analogue conversion | |
US5977899A (en) | Digital-to-analog converter using noise-shaped segmentation | |
US5382955A (en) | Error tolerant thermometer-to-binary encoder | |
US9467161B1 (en) | Low-power, high-speed successive approximation register analog-to-digital converter and conversion method using the same | |
BR9713948A (pt) | Processo para converção de um sinal de entrada digital de um predeterminado número inteiro, n, de bits b (i) em sinal de saìda analógico, conversor digital-para-analógico, e, estágio direcionado para um conversor digital-para-analógico | |
GB2223369A (en) | Analogue-to-digital converters | |
US7205913B2 (en) | Efficient data-directed scrambler for noise-shaping mixed-signal converters | |
US7046181B2 (en) | 2n-1 Shuffling network | |
US5084701A (en) | Digital-to-analog converter using cyclical current source switching | |
US5276446A (en) | Analog-to-digital converter with error signal compensation and method for its operation | |
Vesterbacka et al. | Dynamic element matching in D/A converters with restricted scrambling | |
CN109639276B (zh) | 具有drrz校正功能的双倍时间交织电流舵型dac | |
JPS61292420A (ja) | A/d変換器 | |
US6859387B1 (en) | Three-state binary adders and methods of operating the same | |
USRE34660E (en) | Apparatus and methods for digital-to-analog conversion using modified LSB switching | |
CN112653469B (zh) | 一种混合型sar-adc电路及模数转换方法 | |
SU1697089A1 (ru) | Аналого-цифровой логарифматор-антилогарифматор | |
SU769730A1 (ru) | Устройство преобразовани информации | |
KR880002500B1 (ko) | 16비트용 고속 a/d 콘버터 | |
SU1501268A2 (ru) | Устройство аналого-цифрового преобразовани | |
SU1642587A1 (ru) | Цифроаналоговый преобразователь с усреднением выходного напр жени | |
SU1540001A1 (ru) | Устройство дл поверки цифроаналоговых преобразователей | |
Jensen et al. | Dynamic element matching for highly linear digital-to-analog conversion | |
Solan | f Basic ADC Design and Issue Algorithm | |
Andersson et al. | Partial decomposition of digital-to-analog converters |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
B08F | Application fees: application dismissed [chapter 8.6 patent gazette] |
Free format text: REFERENTE A 7A,8A E 9A ANUIDADES. |
|
B08K | Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette] |
Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1868 DE 24/10/2006. |