BR8706324A - Metodo de projeto fisico de microplaquetas visi e microplaqueta vlsi - Google Patents

Metodo de projeto fisico de microplaquetas visi e microplaqueta vlsi

Info

Publication number
BR8706324A
BR8706324A BR8706324A BR8706324A BR8706324A BR 8706324 A BR8706324 A BR 8706324A BR 8706324 A BR8706324 A BR 8706324A BR 8706324 A BR8706324 A BR 8706324A BR 8706324 A BR8706324 A BR 8706324A
Authority
BR
Brazil
Prior art keywords
chips
visi
design method
physical design
vlsi
Prior art date
Application number
BR8706324A
Other languages
English (en)
Inventor
Klaus Klein
Kurt Pollmann
Helmut Schettler
Uwe Schulz
Otto M Wagner
Rainer Zuehlke
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8706324A publication Critical patent/BR8706324A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
BR8706324A 1986-12-17 1987-11-24 Metodo de projeto fisico de microplaquetas visi e microplaqueta vlsi BR8706324A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP86117601A EP0271596B1 (en) 1986-12-17 1986-12-17 VLSI-chip design and manufacturing process

Publications (1)

Publication Number Publication Date
BR8706324A true BR8706324A (pt) 1988-07-19

Family

ID=8195651

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8706324A BR8706324A (pt) 1986-12-17 1987-11-24 Metodo de projeto fisico de microplaquetas visi e microplaqueta vlsi

Country Status (6)

Country Link
US (1) US4890238A (pt)
EP (1) EP0271596B1 (pt)
JP (1) JPH073841B2 (pt)
BR (1) BR8706324A (pt)
CA (1) CA1275508C (pt)
DE (1) DE3650323T2 (pt)

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US5222030A (en) * 1990-04-06 1993-06-22 Lsi Logic Corporation Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof
US5553002A (en) * 1990-04-06 1996-09-03 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface
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US5513124A (en) * 1991-10-30 1996-04-30 Xilinx, Inc. Logic placement using positionally asymmetrical partitioning method
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US5884065A (en) * 1992-01-10 1999-03-16 Nec Corporation Logic circuit apparatus and method for sequentially performing one of a fault-free simulation and a fault simulation through various levels of a logic circuit
JP2800527B2 (ja) * 1992-02-26 1998-09-21 日本電気株式会社 フロアプラン装置
JP2776120B2 (ja) * 1992-03-10 1998-07-16 日本電気株式会社 集積回路の電源配線布設方法
US5526517A (en) * 1992-05-15 1996-06-11 Lsi Logic Corporation Concurrently operating design tools in an electronic computer aided design system
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
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US5648912A (en) * 1993-04-12 1997-07-15 International Business Machines Corporation Interconnection resource assignment method for differential current switch nets
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US5533148A (en) * 1993-09-30 1996-07-02 International Business Machines Corporation Method for restructuring physical design images into hierarchical data models
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JP2758817B2 (ja) * 1993-12-13 1998-05-28 日本電気株式会社 論理回路実現性判定システム
US5918242A (en) * 1994-03-14 1999-06-29 International Business Machines Corporation General-purpose customizable memory controller
US5818726A (en) * 1994-04-18 1998-10-06 Cadence Design Systems, Inc. System and method for determining acceptable logic cell locations and generating a legal location structure
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US5638288A (en) * 1994-08-24 1997-06-10 Lsi Logic Corporation Separable cells having wiring channels for routing signals between surrounding cells
US5587923A (en) * 1994-09-07 1996-12-24 Lsi Logic Corporation Method for estimating routability and congestion in a cell placement for integrated circuit chip
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US5764532A (en) * 1995-07-05 1998-06-09 International Business Machines Corporation Automated method and system for designing an optimized integrated circuit
US5777383A (en) * 1996-05-09 1998-07-07 Lsi Logic Corporation Semiconductor chip package with interconnect layers and routing and testing methods
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US6091072A (en) * 1997-10-23 2000-07-18 International Business Machines Corporation Piece-wise processing of very large semiconductor designs
US6266802B1 (en) 1997-10-27 2001-07-24 International Business Machines Corporation Detailed grid point layout using a massively parallel logic including an emulator/simulator paradigm
US6000038A (en) * 1997-11-05 1999-12-07 Lsi Logic Corporation Parallel processing of Integrated circuit pin arrival times
US6507938B1 (en) 1999-11-12 2003-01-14 Intel Corporation Methods for improving the performance of VLSI layouts designed by a timing driven physical design tool
US6484302B1 (en) * 2000-07-11 2002-11-19 Hewlett-Packard Company Auto-contactor system and method for generating variable size contacts
JP2002124572A (ja) * 2000-10-18 2002-04-26 Mitsubishi Electric Corp 自動配置配線装置及びそれを用いる配置配線方法
US6857116B1 (en) 2000-11-15 2005-02-15 Reshape, Inc. Optimization of abutted-pin hierarchical physical design
US6792582B1 (en) * 2000-11-15 2004-09-14 International Business Machines Corporation Concurrent logical and physical construction of voltage islands for mixed supply voltage designs
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US6907588B2 (en) * 2002-12-31 2005-06-14 Lsi Logic Corporation Congestion estimation for register transfer level code
US7051307B2 (en) * 2003-12-03 2006-05-23 International Business Machines Corporation Autonomic graphical partitioning
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US7269818B2 (en) * 2005-01-06 2007-09-11 International Business Machines Corporation Circuit element function matching despite auto-generated dummy shapes
TWI381282B (zh) * 2008-11-13 2013-01-01 Mstar Semiconductor Inc 防止壅塞配置方法及裝置
US8782586B2 (en) * 2009-07-16 2014-07-15 Cadence Design Systems, Inc. Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterning
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FR2963687A1 (fr) 2010-08-06 2012-02-10 Dolphin Integration Sa Arbre d'horloge pour bascules commandees par impulsions
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US4608649A (en) * 1983-06-27 1986-08-26 International Business Machines Corporation Differential cascode voltage switch (DCVS) master slice for high efficiency/custom density physical design
US4593363A (en) * 1983-08-12 1986-06-03 International Business Machines Corporation Simultaneous placement and wiring for VLSI chips
US4577276A (en) * 1983-09-12 1986-03-18 At&T Bell Laboratories Placement of components on circuit substrates
US4630219A (en) * 1983-11-23 1986-12-16 International Business Machines Corporation Element placement method
JPS60136332A (ja) * 1983-12-26 1985-07-19 Hitachi Ltd 半導体装置
US4713773A (en) * 1984-08-10 1987-12-15 International Business Machine Corporation Method for distributing wire load in a multilayer package and the resulting product

Also Published As

Publication number Publication date
DE3650323D1 (de) 1995-06-22
EP0271596A1 (en) 1988-06-22
EP0271596B1 (en) 1995-05-17
JPS63156336A (ja) 1988-06-29
CA1275508C (en) 1990-10-23
US4890238A (en) 1989-12-26
JPH073841B2 (ja) 1995-01-18
DE3650323T2 (de) 1996-01-25

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Legal Events

Date Code Title Description
MM Lapse due to non-payment of fees (art. 50)
B15K Others concerning applications: alteration of classification

Ipc: G06F 17/50 (2006.01)