BR8705230A - Processos de aplanamento atraves de sililacao e de fabricacao de pinos para interconexao de camadas de metalizacao em diferentes niveis em uma microplaqueta semicondutora - Google Patents
Processos de aplanamento atraves de sililacao e de fabricacao de pinos para interconexao de camadas de metalizacao em diferentes niveis em uma microplaqueta semicondutoraInfo
- Publication number
- BR8705230A BR8705230A BR8705230A BR8705230A BR8705230A BR 8705230 A BR8705230 A BR 8705230A BR 8705230 A BR8705230 A BR 8705230A BR 8705230 A BR8705230 A BR 8705230A BR 8705230 A BR8705230 A BR 8705230A
- Authority
- BR
- Brazil
- Prior art keywords
- sililation
- semiconductor chip
- different levels
- application processes
- metalization layers
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
- G03F7/162—Coating on a rotating support, e.g. using a whirler or a spinner
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/06—Planarisation of inorganic insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/923,779 US4816112A (en) | 1986-10-27 | 1986-10-27 | Planarization process through silylation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BR8705230A true BR8705230A (pt) | 1988-05-24 |
Family
ID=25449260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BR8705230A BR8705230A (pt) | 1986-10-27 | 1987-10-02 | Processos de aplanamento atraves de sililacao e de fabricacao de pinos para interconexao de camadas de metalizacao em diferentes niveis em uma microplaqueta semicondutora |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4816112A (https=) |
| EP (1) | EP0265619B1 (https=) |
| JP (1) | JPS63115341A (https=) |
| AU (1) | AU594518B2 (https=) |
| BR (1) | BR8705230A (https=) |
| CA (1) | CA1308609C (https=) |
| DE (1) | DE3779043D1 (https=) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4986876A (en) * | 1990-05-07 | 1991-01-22 | The United States Of America As Represented By The Secretary Of The Army | Method of smoothing patterned transparent electrode stripes in thin film electroluminescent display panel manufacture |
| US5139608A (en) * | 1991-04-01 | 1992-08-18 | Motorola, Inc. | Method of planarizing a semiconductor device surface |
| JPH05243223A (ja) * | 1992-02-28 | 1993-09-21 | Fujitsu Ltd | 集積回路装置の製造方法 |
| KR0170253B1 (ko) * | 1992-11-18 | 1999-03-20 | 김광호 | 실리레이션을 이용한 사진식각방법 |
| US5981143A (en) * | 1997-11-26 | 1999-11-09 | Trw Inc. | Chemically treated photoresist for withstanding ion bombarded processing |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2547792C3 (de) * | 1974-10-25 | 1978-08-31 | Hitachi, Ltd., Tokio | Verfahren zur Herstellung eines Halbleiterbauelementes |
| US4004044A (en) * | 1975-05-09 | 1977-01-18 | International Business Machines Corporation | Method for forming patterned films utilizing a transparent lift-off mask |
| EP0117258B1 (de) * | 1983-02-23 | 1987-05-20 | Ibm Deutschland Gmbh | Verfahren zur Herstellung von haftfesten Metallschichten auf Kunststoffsubstraten |
| GB2153335B (en) * | 1983-07-20 | 1988-05-25 | Don Marketing Management Ltd | A label |
| US4511430A (en) * | 1984-01-30 | 1985-04-16 | International Business Machines Corporation | Control of etch rate ratio of SiO2 /photoresist for quartz planarization etch back process |
| US4552833A (en) * | 1984-05-14 | 1985-11-12 | International Business Machines Corporation | Radiation sensitive and oxygen plasma developable resist |
| JPS60262150A (ja) * | 1984-06-11 | 1985-12-25 | Nippon Telegr & Teleph Corp <Ntt> | 三層レジスト用中間層材料及びそれを用いた三層レジストパタン形成方法 |
| US4541168A (en) * | 1984-10-29 | 1985-09-17 | International Business Machines Corporation | Method for making metal contact studs between first level metal and regions of a semiconductor device compatible with polyimide-filled deep trench isolation schemes |
| US4541169A (en) * | 1984-10-29 | 1985-09-17 | International Business Machines Corporation | Method for making studs for interconnecting metallization layers at different levels in a semiconductor chip |
| US4613398A (en) * | 1985-06-06 | 1986-09-23 | International Business Machines Corporation | Formation of etch-resistant resists through preferential permeation |
| US4702792A (en) * | 1985-10-28 | 1987-10-27 | International Business Machines Corporation | Method of forming fine conductive lines, patterns and connectors |
| US4944836A (en) * | 1985-10-28 | 1990-07-31 | International Business Machines Corporation | Chem-mech polishing method for producing coplanar metal/insulator films on a substrate |
| US4723978A (en) * | 1985-10-31 | 1988-02-09 | International Business Machines Corporation | Method for a plasma-treated polysiloxane coating |
| US4676868A (en) * | 1986-04-23 | 1987-06-30 | Fairchild Semiconductor Corporation | Method for planarizing semiconductor substrates |
-
1986
- 1986-10-27 US US06/923,779 patent/US4816112A/en not_active Expired - Fee Related
-
1987
- 1987-07-16 JP JP62176104A patent/JPS63115341A/ja active Granted
- 1987-08-25 EP EP87112330A patent/EP0265619B1/en not_active Expired - Lifetime
- 1987-08-25 DE DE8787112330T patent/DE3779043D1/de not_active Expired - Lifetime
- 1987-10-02 BR BR8705230A patent/BR8705230A/pt not_active IP Right Cessation
- 1987-10-13 CA CA000549182A patent/CA1308609C/en not_active Expired - Lifetime
- 1987-10-26 AU AU80131/87A patent/AU594518B2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| US4816112A (en) | 1989-03-28 |
| EP0265619A3 (en) | 1988-10-26 |
| EP0265619A2 (en) | 1988-05-04 |
| CA1308609C (en) | 1992-10-13 |
| JPH0565049B2 (https=) | 1993-09-16 |
| EP0265619B1 (en) | 1992-05-13 |
| DE3779043D1 (de) | 1992-06-17 |
| AU8013187A (en) | 1988-05-05 |
| JPS63115341A (ja) | 1988-05-19 |
| AU594518B2 (en) | 1990-03-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FG | Letter patent granted | ||
| B21A | Patent or certificate of addition expired [chapter 21.1 patent gazette] |
Free format text: PATENTE EXTINTA EM 02/10/2002 |
|
| B15K | Others concerning applications: alteration of classification |
Ipc: G03F 7/16 (2006.01), H01L 21/3105 (2006.0 |