BR8205588A - Sistema de processamento de erro de armazenamento de chave - Google Patents

Sistema de processamento de erro de armazenamento de chave

Info

Publication number
BR8205588A
BR8205588A BR8205588A BR8205588A BR8205588A BR 8205588 A BR8205588 A BR 8205588A BR 8205588 A BR8205588 A BR 8205588A BR 8205588 A BR8205588 A BR 8205588A BR 8205588 A BR8205588 A BR 8205588A
Authority
BR
Brazil
Prior art keywords
bit
key
processing system
error processing
key storage
Prior art date
Application number
BR8205588A
Other languages
English (en)
Inventor
Terutaka Tateishi
Kazuyuki Shimizu
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of BR8205588A publication Critical patent/BR8205588A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1466—Key-lock mechanism
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Human Computer Interaction (AREA)
  • Storage Device Security (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Detection And Correction Of Errors (AREA)
BR8205588A 1981-09-24 1982-09-23 Sistema de processamento de erro de armazenamento de chave BR8205588A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56151046A JPS5853097A (ja) 1981-09-24 1981-09-24 キ−記憶のエラ−処理方式

Publications (1)

Publication Number Publication Date
BR8205588A true BR8205588A (pt) 1983-08-30

Family

ID=15510109

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8205588A BR8205588A (pt) 1981-09-24 1982-09-23 Sistema de processamento de erro de armazenamento de chave

Country Status (8)

Country Link
US (1) US4514847A (pt)
EP (1) EP0076098B1 (pt)
JP (1) JPS5853097A (pt)
KR (1) KR860002027B1 (pt)
AU (1) AU537967B2 (pt)
BR (1) BR8205588A (pt)
CA (1) CA1183608A (pt)
DE (1) DE3274686D1 (pt)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62293599A (ja) * 1986-06-13 1987-12-21 Hitachi Ltd 半導体記憶装置
US5031179A (en) * 1987-11-10 1991-07-09 Canon Kabushiki Kaisha Data communication apparatus
US4916703A (en) * 1988-11-28 1990-04-10 International Business Machines Corporation Handling errors in the C bit of a storage key
JP3786993B2 (ja) * 1995-12-14 2006-06-21 株式会社日立製作所 データ記憶ユニット及び該ユニットを用いたデータ記憶装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4053752A (en) * 1975-09-15 1977-10-11 International Business Machines Corporation Error recovery and control in a mass storage system
US4020459A (en) * 1975-10-28 1977-04-26 Bell Telephone Laboratories, Incorporated Parity generation and bus matching arrangement for synchronized duplicated data processing units
US4146099A (en) * 1976-08-17 1979-03-27 Christopher Scientific Company Signal recording method and apparatus
US4103823A (en) * 1976-12-20 1978-08-01 International Business Machines Corporation Parity checking scheme for detecting word line failure in multiple byte arrays
US4084236A (en) * 1977-02-18 1978-04-11 Honeywell Information Systems Inc. Error detection and correction capability for a memory system
US4092713A (en) * 1977-06-13 1978-05-30 Sperry Rand Corporation Post-write address word correction in cache memory system
US4266272A (en) * 1978-10-12 1981-05-05 International Business Machines Corporation Transient microcode block check word generation control circuitry

Also Published As

Publication number Publication date
EP0076098A3 (en) 1984-10-03
DE3274686D1 (en) 1987-01-22
AU537967B2 (en) 1984-07-19
US4514847A (en) 1985-04-30
AU8841582A (en) 1983-03-31
KR860002027B1 (ko) 1986-11-15
JPS6136670B2 (pt) 1986-08-19
CA1183608A (en) 1985-03-05
JPS5853097A (ja) 1983-03-29
EP0076098B1 (en) 1986-12-10
KR840001726A (ko) 1984-05-16
EP0076098A2 (en) 1983-04-06

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Legal Events

Date Code Title Description
B21A Patent or certificate of addition expired [chapter 21.1 patent gazette]

Free format text: PATENTE EXTINTA EM 23/09/97