BR7904451A - Aparelho de traducao de endereco - Google Patents

Aparelho de traducao de endereco

Info

Publication number
BR7904451A
BR7904451A BR7904451A BR7904451A BR7904451A BR 7904451 A BR7904451 A BR 7904451A BR 7904451 A BR7904451 A BR 7904451A BR 7904451 A BR7904451 A BR 7904451A BR 7904451 A BR7904451 A BR 7904451A
Authority
BR
Brazil
Prior art keywords
address translation
translation apparatus
address
translation
Prior art date
Application number
BR7904451A
Other languages
English (en)
Inventor
F Soltis
G Mitchell
R Hoffman
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR7904451A publication Critical patent/BR7904451A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G06F12/1018—Address translation using page tables, e.g. page table structures involving hashing techniques, e.g. inverted page tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
BR7904451A 1978-07-17 1979-07-12 Aparelho de traducao de endereco BR7904451A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/925,490 US4218743A (en) 1978-07-17 1978-07-17 Address translation apparatus

Publications (1)

Publication Number Publication Date
BR7904451A true BR7904451A (pt) 1980-04-08

Family

ID=25451802

Family Applications (1)

Application Number Title Priority Date Filing Date
BR7904451A BR7904451A (pt) 1978-07-17 1979-07-12 Aparelho de traducao de endereco

Country Status (5)

Country Link
US (1) US4218743A (pt)
EP (1) EP0007003B1 (pt)
JP (1) JPS5514598A (pt)
BR (1) BR7904451A (pt)
DE (1) DE2963099D1 (pt)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2472231B1 (fr) * 1979-12-20 1986-02-21 Cii Honeywell Bull Dispositif d'adressage d'elements d'informations dans une table a plusieurs entrees, enregistree dans une memoire
US4320456A (en) * 1980-01-18 1982-03-16 International Business Machines Corporation Control apparatus for virtual address translation unit
US4507781A (en) * 1980-03-14 1985-03-26 Ibm Corporation Time domain multiple access broadcasting, multipoint, and conferencing communication apparatus and method
US4332010A (en) * 1980-03-17 1982-05-25 International Business Machines Corporation Cache synonym detection and handling mechanism
US4356549A (en) * 1980-04-02 1982-10-26 Control Data Corporation System page table apparatus
US4403283A (en) * 1980-07-28 1983-09-06 Ncr Corporation Extended memory system and method
JPS5734251A (en) * 1980-08-07 1982-02-24 Toshiba Corp Address conversion and generating system
US4482952A (en) * 1980-12-15 1984-11-13 Nippon Electric Co., Ltd. Virtual addressing system using page field comparisons to selectively validate cache buffer data on read main memory data
US4455604A (en) * 1981-05-22 1984-06-19 Data General Corporation Digital data processing system having addressing means for translating operands into descriptors identifying data, plural multilevel microcode control means, and ability to execute a plurality of internal language dialects
JPS6047623B2 (ja) * 1982-02-12 1985-10-22 株式会社日立製作所 アドレス変換方式
JPS59100545U (ja) * 1982-12-27 1984-07-06 日野自動車株式会社 製造指示カ−ド
US4638426A (en) * 1982-12-30 1987-01-20 International Business Machines Corporation Virtual memory address translation mechanism with controlled data persistence
US4574351A (en) * 1983-03-03 1986-03-04 International Business Machines Corporation Apparatus for compressing and buffering data
US4642755A (en) * 1983-03-31 1987-02-10 At&T Bell Laboratories Shared memory with two distinct addressing structures
JPS6022247U (ja) * 1983-07-21 1985-02-15 マツダ株式会社 加工ラインにおけるワ−ク読取り装置
US4682281A (en) * 1983-08-30 1987-07-21 Amdahl Corporation Data storage unit employing translation lookaside buffer pointer
US4612612A (en) * 1983-08-30 1986-09-16 Amdahl Corporation Virtually addressed cache
US4727482A (en) * 1983-08-30 1988-02-23 Amdahl Corporation Apparatus for enhancing searches of data tables
US4551797A (en) * 1983-08-31 1985-11-05 Amdahl Corporation Apparatus for reverse translation
CH662546A5 (de) * 1983-09-05 1987-10-15 Ferag Ag Verfahren und vorrichtung zum verarbeiten von von einem speicherwickel abgewickelten flaechigen erzeugnissen, insbesondere druckprodukten.
US4654790A (en) * 1983-11-28 1987-03-31 Amdahl Corporation Translation of virtual and real addresses to system addresses
US4680700A (en) * 1983-12-07 1987-07-14 International Business Machines Corporation Virtual memory address translation mechanism with combined hash address table and inverted page table
JPH0656594B2 (ja) * 1985-05-07 1994-07-27 株式会社日立製作所 ベクトルプロセツサ
US4722047A (en) * 1985-08-29 1988-01-26 Ncr Corporation Prefetch circuit and associated method for operation with a virtual command emulator
US4837738A (en) * 1986-11-05 1989-06-06 Honeywell Information Systems Inc. Address boundary detector
US4914577A (en) * 1987-07-16 1990-04-03 Icon International, Inc. Dynamic memory management system and method
JPH07120312B2 (ja) * 1987-10-07 1995-12-20 株式会社日立製作所 バッファメモリ制御装置
US4903194A (en) * 1987-11-12 1990-02-20 International Business Machines Corporation Storage addressing error detection circuitry
JP2589713B2 (ja) * 1987-11-20 1997-03-12 株式会社日立製作所 データプロセッサ及びデータ処理システム
JP2722523B2 (ja) * 1988-09-21 1998-03-04 日本電気株式会社 命令先取り装置
US4888727A (en) * 1989-01-10 1989-12-19 Bull Hn Information Systems Inc. Peripheral controller with paged data buffer management
US5099415A (en) * 1989-02-15 1992-03-24 International Business Machines Guess mechanism for virtual address translation
US5226133A (en) * 1989-12-01 1993-07-06 Silicon Graphics, Inc. Two-level translation look-aside buffer using partial addresses for enhanced speed
JPH06231047A (ja) * 1993-02-05 1994-08-19 Fujitsu Ltd アドレス変換方法および装置
US5502829A (en) * 1993-11-03 1996-03-26 Intergraph Corporation Apparatus for obtaining data from a translation memory based on carry signal from adder
US5721947A (en) * 1995-05-15 1998-02-24 Nvidia Corporation Apparatus adapted to be joined between the system I/O bus and I/O devices which translates addresses furnished directly by an application program
US5991854A (en) * 1996-07-01 1999-11-23 Sun Microsystems, Inc. Circuit and method for address translation, using update and flush control circuits
US7653803B2 (en) * 2006-01-17 2010-01-26 Globalfoundries Inc. Address translation for input/output (I/O) devices and interrupt remapping for I/O devices in an I/O memory management unit (IOMMU)
GB2570665B (en) * 2018-01-31 2020-08-26 Advanced Risc Mach Ltd Address translation in a data processing apparatus

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR10582E (fr) * 1970-06-29 1909-07-30 Paul Alexis Victor Lerolle Jeu de serrures avec passe-partout
DE2134816C3 (de) * 1971-07-13 1978-04-27 Ibm Deutschland Gmbh, 7000 Stuttgart Einrichtung zur Adressenübersetzung
US3902164A (en) * 1972-07-21 1975-08-26 Ibm Method and means for reducing the amount of address translation in a virtual memory data processing system
US4010451A (en) * 1972-10-03 1977-03-01 National Research Development Corporation Data structure processor
US3854126A (en) * 1972-10-10 1974-12-10 Digital Equipment Corp Circuit for converting virtual addresses into physical addresses
US3781808A (en) * 1972-10-17 1973-12-25 Ibm Virtual memory system
JPS532296B2 (pt) * 1973-03-19 1978-01-26
FR122199A (pt) * 1973-12-17
US3938100A (en) * 1974-06-07 1976-02-10 Control Data Corporation Virtual addressing apparatus for addressing the memory of a computer utilizing associative addressing techniques
JPS5615066B2 (pt) * 1974-06-13 1981-04-08
AU506710B2 (en) * 1974-10-21 1980-01-24 Honeywell Information Systems Incorp. Method of accessing priviledged memory in a multiprogrammed data processing system
DE2601379C3 (de) * 1976-01-15 1980-11-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zum Umwandeln virtueller Adressen in reelle Adressen
US4048671A (en) * 1976-06-30 1977-09-13 Ibm Corporation Address match for data processing system with virtual addressing

Also Published As

Publication number Publication date
EP0007003A1 (en) 1980-01-23
DE2963099D1 (en) 1982-08-05
US4218743A (en) 1980-08-19
EP0007003B1 (en) 1982-06-16
JPS5514598A (en) 1980-02-01
JPS5723952B2 (pt) 1982-05-21

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Legal Events

Date Code Title Description
MK Patent expired

Effective date: 19940712