BR7406340D0 - Dispositivo semi-condutor e seu processo de fabricacao - Google Patents
Dispositivo semi-condutor e seu processo de fabricacaoInfo
- Publication number
- BR7406340D0 BR7406340D0 BR6340/74A BR634074A BR7406340D0 BR 7406340 D0 BR7406340 D0 BR 7406340D0 BR 6340/74 A BR6340/74 A BR 6340/74A BR 634074 A BR634074 A BR 634074A BR 7406340 D0 BR7406340 D0 BR 7406340D0
- Authority
- BR
- Brazil
- Prior art keywords
- semi
- manufacturing process
- conductor device
- conductor
- manufacturing
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US38566973A | 1973-08-06 | 1973-08-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
BR7406340D0 true BR7406340D0 (pt) | 1975-09-09 |
Family
ID=23522380
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR6340/74A BR7406340D0 (pt) | 1973-08-06 | 1974-08-02 | Dispositivo semi-condutor e seu processo de fabricacao |
Country Status (12)
Country | Link |
---|---|
US (1) | US4069577A (pt) |
JP (1) | JPS5051276A (pt) |
BE (1) | BE818547A (pt) |
BR (1) | BR7406340D0 (pt) |
CA (1) | CA1012658A (pt) |
DE (1) | DE2436517A1 (pt) |
FR (1) | FR2240532B1 (pt) |
GB (1) | GB1476790A (pt) |
IN (1) | IN140846B (pt) |
IT (1) | IT1015392B (pt) |
NL (1) | NL7410214A (pt) |
SE (1) | SE7409993L (pt) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5075775A (pt) * | 1973-11-06 | 1975-06-21 | ||
JPS5918872B2 (ja) * | 1973-12-07 | 1984-05-01 | 日本電気株式会社 | 絶縁ゲ−ト型電界効果半導体装置の製法 |
JPS5293278A (en) * | 1976-01-30 | 1977-08-05 | Matsushita Electronics Corp | Manufacture for mos type semiconductor intergrated circuit |
JPS52117079A (en) * | 1976-03-29 | 1977-10-01 | Oki Electric Ind Co Ltd | Preparation of semiconductor device |
FR2351502A1 (fr) * | 1976-05-14 | 1977-12-09 | Ibm | Procede de fabrication de transistors a effet de champ a porte en silicium polycristallin auto-alignee avec les regions source et drain ainsi qu'avec les regions d'isolation de champ encastrees |
US4035198A (en) * | 1976-06-30 | 1977-07-12 | International Business Machines Corporation | Method of fabricating field effect transistors having self-registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors |
US4095251A (en) * | 1976-08-19 | 1978-06-13 | International Business Machines Corporation | Field effect transistors and fabrication of integrated circuits containing the transistors |
JPS5464480A (en) * | 1977-10-31 | 1979-05-24 | Nec Corp | Semiconductor device |
JPS54109784A (en) * | 1978-02-16 | 1979-08-28 | Nec Corp | Manufacture of semiconductor device |
JPS5848936A (ja) * | 1981-09-10 | 1983-03-23 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS59123266A (ja) * | 1982-12-28 | 1984-07-17 | Toshiba Corp | Misトランジスタ及びその製造方法 |
US5798291A (en) * | 1995-03-20 | 1998-08-25 | Lg Semicon Co., Ltd. | Method of making a semiconductor device with recessed source and drain |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3691627A (en) * | 1970-02-03 | 1972-09-19 | Gen Electric | Method of fabricating buried metallic film devices |
US3673471A (en) * | 1970-10-08 | 1972-06-27 | Fairchild Camera Instr Co | Doped semiconductor electrodes for mos type devices |
US3761327A (en) * | 1971-03-19 | 1973-09-25 | Itt | Planar silicon gate mos process |
NL7113561A (pt) * | 1971-10-02 | 1973-04-04 | ||
CA1001771A (en) * | 1973-01-15 | 1976-12-14 | Fairchild Camera And Instrument Corporation | Method of mos transistor manufacture and resulting structure |
-
1974
- 1974-06-11 IN IN1265/CAL/1974A patent/IN140846B/en unknown
- 1974-06-25 IT IT24412/74A patent/IT1015392B/it active
- 1974-07-15 CA CA204,805A patent/CA1012658A/en not_active Expired
- 1974-07-29 GB GB3331574A patent/GB1476790A/en not_active Expired
- 1974-07-29 DE DE2436517A patent/DE2436517A1/de active Pending
- 1974-07-30 NL NL7410214A patent/NL7410214A/xx unknown
- 1974-08-02 SE SE7409993A patent/SE7409993L/xx unknown
- 1974-08-02 BR BR6340/74A patent/BR7406340D0/pt unknown
- 1974-08-02 JP JP49089408A patent/JPS5051276A/ja active Pending
- 1974-08-05 FR FR7427142A patent/FR2240532B1/fr not_active Expired
- 1974-08-06 BE BE147341A patent/BE818547A/xx unknown
-
1975
- 1975-04-22 US US05/570,433 patent/US4069577A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US4069577A (en) | 1978-01-24 |
IT1015392B (it) | 1977-05-10 |
DE2436517A1 (de) | 1975-03-06 |
BE818547A (fr) | 1974-12-02 |
JPS5051276A (pt) | 1975-05-08 |
FR2240532B1 (pt) | 1978-08-11 |
IN140846B (pt) | 1976-12-25 |
NL7410214A (nl) | 1975-02-10 |
FR2240532A1 (pt) | 1975-03-07 |
GB1476790A (en) | 1977-06-16 |
CA1012658A (en) | 1977-06-21 |
AU7206174A (en) | 1976-02-12 |
SE7409993L (pt) | 1975-02-07 |
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