BR112018004935A2 - dispositivo e método passivo em vidro (pog) - Google Patents

dispositivo e método passivo em vidro (pog)

Info

Publication number
BR112018004935A2
BR112018004935A2 BR112018004935A BR112018004935A BR112018004935A2 BR 112018004935 A2 BR112018004935 A2 BR 112018004935A2 BR 112018004935 A BR112018004935 A BR 112018004935A BR 112018004935 A BR112018004935 A BR 112018004935A BR 112018004935 A2 BR112018004935 A2 BR 112018004935A2
Authority
BR
Brazil
Prior art keywords
pog
glass device
passive glass
capacitor
electrode
Prior art date
Application number
BR112018004935A
Other languages
English (en)
Other versions
BR112018004935B1 (pt
Inventor
Hobie Yun Changhan
Zuo Chengjie
Daniel Kim Daeik
Francis Berdy David
Jeffrey Lan Je-Hsiung
Kim Jonghae
Francisco Velez Mario
Sunil Mudakatte Niranjan
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018004935A2 publication Critical patent/BR112018004935A2/pt
Publication of BR112018004935B1 publication Critical patent/BR112018004935B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02—Mountings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

um dispositivo inclui um substrato de vidro e um capacitor. o capacitor inclui um primeiro metal acoplado a um primeiro eletrodo, uma estrutura dielétrica, e uma estrutura de passagem compreendendo um segundo eletrodo do capacitor. a primeira estrutura metálica é separada da estrutura de passagem através da estrutura dielétrica.
BR112018004935-2A 2015-09-14 2016-07-29 Dispositivo e método passivo em vidro (pog) BR112018004935B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/853,701 2015-09-14
US14/853,701 US9893048B2 (en) 2015-09-14 2015-09-14 Passive-on-glass (POG) device and method
PCT/US2016/044865 WO2017048379A1 (en) 2015-09-14 2016-07-29 Passive-on-glass (pog) device and method

Publications (2)

Publication Number Publication Date
BR112018004935A2 true BR112018004935A2 (pt) 2018-10-09
BR112018004935B1 BR112018004935B1 (pt) 2023-02-23

Family

ID=56799534

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018004935-2A BR112018004935B1 (pt) 2015-09-14 2016-07-29 Dispositivo e método passivo em vidro (pog)

Country Status (7)

Country Link
US (2) US9893048B2 (pt)
EP (1) EP3350832A1 (pt)
JP (2) JP2018534763A (pt)
KR (1) KR101995955B1 (pt)
CN (1) CN108028244A (pt)
BR (1) BR112018004935B1 (pt)
WO (1) WO2017048379A1 (pt)

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US10510828B2 (en) 2016-10-04 2019-12-17 Nano Henry, Inc. Capacitor with high aspect radio silicon cores
US10872950B2 (en) 2016-10-04 2020-12-22 Nanohenry Inc. Method for growing very thick thermal local silicon oxide structures and silicon oxide embedded spiral inductors
US10833144B2 (en) 2016-11-14 2020-11-10 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including an inductor and a capacitor
US10157871B1 (en) * 2017-10-12 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and manufacturing method thereof
JP7139594B2 (ja) * 2017-11-30 2022-09-21 凸版印刷株式会社 ガラスコア、多層配線基板、及びガラスコアの製造方法
DE102017130924B3 (de) 2017-12-21 2019-05-16 RF360 Europe GmbH Hybridfilter
DE102017130926A1 (de) 2017-12-21 2019-06-27 RF360 Europe GmbH Waferanordnung, Verfahren zur Fertigung von derselben und Hybridfilter
US10811370B2 (en) * 2018-04-24 2020-10-20 Cree, Inc. Packaged electronic circuits having moisture protection encapsulation and methods of forming same
US10840884B2 (en) * 2018-05-24 2020-11-17 Qualcomm Incorporated Bulk acoustic wave (BAW) and passive-on-glass (POG) filter co-integration
US10700159B2 (en) * 2018-06-27 2020-06-30 Intel IP Corporation Method of providing partial electrical shielding
US10741702B2 (en) 2018-10-08 2020-08-11 Qualcomm Incorporated Thin-film variable metal-oxide-semiconductor (MOS) capacitor for passive-on-glass (POG) tunable capacitor
US11152272B2 (en) 2019-11-13 2021-10-19 Qualcomm Incorporated Die-to-wafer hybrid bonding with forming glass
US11177065B2 (en) * 2020-03-30 2021-11-16 Qualcomm Incorporated Thermal paths for glass substrates
US11404345B2 (en) 2020-06-10 2022-08-02 Qualcomm Incorporated Advanced integrated passive device (IPD) with thin-film heat spreader (TF-HS) layer for high power handling filters in transmit (TX) path
CN112312654B (zh) * 2020-08-14 2021-09-17 珠海越亚半导体股份有限公司 一种嵌埋在玻璃介质中的无源器件结构及其制造方法
US11770115B2 (en) * 2020-10-16 2023-09-26 Qualcomm Incorporated Tunable circuit including integrated filter circuit coupled to variable capacitance, and related integrated circuit (IC) packages and fabrication methods
US11728293B2 (en) 2021-02-03 2023-08-15 Qualcomm Incorporated Chip modules employing conductive pillars to couple a passive component device to conductive traces in a metallization structure to form a passive component

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Also Published As

Publication number Publication date
JP2018534763A (ja) 2018-11-22
WO2017048379A1 (en) 2017-03-23
CN108028244A (zh) 2018-05-11
US20170077079A1 (en) 2017-03-16
KR20180042448A (ko) 2018-04-25
EP3350832A1 (en) 2018-07-25
JP2019083352A (ja) 2019-05-30
US9893048B2 (en) 2018-02-13
US20180145062A1 (en) 2018-05-24
US10607980B2 (en) 2020-03-31
KR101995955B1 (ko) 2019-07-03
BR112018004935B1 (pt) 2023-02-23

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 29/07/2016, OBSERVADAS AS CONDICOES LEGAIS