BR112018001409A2 - equalização dependente de tempo para transmissor c-phy trifásico - Google Patents

equalização dependente de tempo para transmissor c-phy trifásico

Info

Publication number
BR112018001409A2
BR112018001409A2 BR112018001409A BR112018001409A BR112018001409A2 BR 112018001409 A2 BR112018001409 A2 BR 112018001409A2 BR 112018001409 A BR112018001409 A BR 112018001409A BR 112018001409 A BR112018001409 A BR 112018001409A BR 112018001409 A2 BR112018001409 A2 BR 112018001409A2
Authority
BR
Brazil
Prior art keywords
symbol
phase
wire
wire interface
transmitted
Prior art date
Application number
BR112018001409A
Other languages
English (en)
Inventor
Lee Chulkyu
Sejpal Dhaval
Alan Wiley George
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018001409A2 publication Critical patent/BR112018001409A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/54—Systems for transmission via power distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/46—Monitoring; Testing
    • H04B3/462—Testing group delay or phase shift, e.g. timing jitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H04L25/0286—Provision of wave shaping within the driver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

um método, um aparelho e um produto de programa de computador para comunicação de dados sobre uma interface multi-fio, multi-fase é fornecido. o método pode incluir fornecer uma sequência de símbolos a serem transmitidos em uma interface de 3 fios, cada símbolo na sequência de símbolos definindo um dos três estados de voltagem para cada fio da interface de 3 fios, acionar todos os fios da interface de 3 fios para um estado de voltagem comum durante uma transição de um primeiro símbolo transmitido para um segundo símbolo transmitido, acionando cada fio da interface de 3 fios de acordo com o segundo símbolo transmitido após um retardo predeterminado. cada fio pode estar em um estado de voltagem diferente dos outros fios da interface de 3 fios durante a transmissão de cada símbolo. o estado de voltagem comum pode situar-se entre dois dos três estados de voltagem.
BR112018001409A 2015-07-24 2016-06-27 equalização dependente de tempo para transmissor c-phy trifásico BR112018001409A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/808,272 US9553635B1 (en) 2015-07-24 2015-07-24 Time based equalization for a C-PHY 3-phase transmitter
PCT/US2016/039667 WO2017019223A1 (en) 2015-07-24 2016-06-27 Time based equalization for a c-phy 3-phase transmitter

Publications (1)

Publication Number Publication Date
BR112018001409A2 true BR112018001409A2 (pt) 2018-09-11

Family

ID=56561427

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018001409A BR112018001409A2 (pt) 2015-07-24 2016-06-27 equalização dependente de tempo para transmissor c-phy trifásico

Country Status (7)

Country Link
US (1) US9553635B1 (pt)
EP (1) EP3326340B1 (pt)
JP (1) JP2018525902A (pt)
KR (1) KR20180033190A (pt)
CN (1) CN107852382B (pt)
BR (1) BR112018001409A2 (pt)
WO (1) WO2017019223A1 (pt)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9711041B2 (en) 2012-03-16 2017-07-18 Qualcomm Incorporated N-phase polarity data transfer
US8064535B2 (en) * 2007-03-02 2011-11-22 Qualcomm Incorporated Three phase and polarity encoded serial interface
US9231790B2 (en) 2007-03-02 2016-01-05 Qualcomm Incorporated N-phase phase and polarity encoded serial interface
FR3046475B1 (fr) 2016-01-04 2018-01-12 Laoviland Experience Procede d'assistance a la manipulation d'au moins n variables de traitement graphique d'images
US9722822B1 (en) * 2016-03-04 2017-08-01 Inphi Corporation Method and system using driver equalization in transmission line channels with power or ground terminations
US9819523B2 (en) * 2016-03-09 2017-11-14 Qualcomm Incorporated Intelligent equalization for a three-transmitter multi-phase system
US10742390B2 (en) * 2016-07-13 2020-08-11 Novatek Microelectronics Corp. Method of improving clock recovery and related device
KR101921119B1 (ko) 2016-07-19 2018-12-06 주식회사 지엠케이 비동기 디지털 통신 모듈
US10419246B2 (en) * 2016-08-31 2019-09-17 Qualcomm Incorporated C-PHY training pattern for adaptive equalization, adaptive edge tracking and delay calibration
TW201830940A (zh) * 2017-02-08 2018-08-16 陳淑玲 三線式傳輸的穿戴裝置
US10560290B2 (en) * 2018-01-08 2020-02-11 Dell Products L.P. Information handling system half unit interval equalization
US10313068B1 (en) 2018-04-24 2019-06-04 Qualcomm Incorporated Signal monitoring and measurement for a multi-wire, multi-phase interface
US10333690B1 (en) 2018-05-04 2019-06-25 Qualcomm Incorporated Calibration pattern and duty-cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface
US10263766B1 (en) 2018-06-11 2019-04-16 Qualcomm Incorporated Independent pair 3-phase eye sampling circuit
US10454725B1 (en) * 2018-09-27 2019-10-22 Qualcomm Incorporated C-PHY receiver equalization
KR20210050193A (ko) 2019-10-28 2021-05-07 삼성전자주식회사 출력 드라이버 및 이를 구비하는 반도체 메모리 장치
US11240077B2 (en) 2019-10-29 2022-02-01 Qualcomm Incorporated C-PHY half-rate wire state encoder and decoder
US11463233B2 (en) 2020-05-21 2022-10-04 Qualcomm Incorporated Unit interval jitter improvement in a C-PHY interface
KR102585148B1 (ko) * 2020-12-09 2023-10-06 주식회사 블라썸테크놀로지 Mipi c-phy 심볼 디코딩 시스템 및 방법
US11545980B1 (en) * 2021-09-08 2023-01-03 Qualcomm Incorporated Clock and data recovery for multi-phase, multi-level encoding
KR102513739B1 (ko) * 2021-10-26 2023-03-27 주식회사 블라썸테크놀로지 Mipi d-phy 고속 송신기의 이퀄라이징 시스템
CN114866098B (zh) * 2022-07-04 2022-10-11 奉加微电子（昆山）有限公司 串行发射机及其前馈均衡电路的压降补偿电路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9231790B2 (en) 2007-03-02 2016-01-05 Qualcomm Incorporated N-phase phase and polarity encoded serial interface
US8996740B2 (en) * 2012-06-29 2015-03-31 Qualcomm Incorporated N-phase polarity output pin mode multiplexer
US9172426B2 (en) 2013-03-07 2015-10-27 Qualcomm Incorporated Voltage mode driver circuit for N-phase systems
US9137008B2 (en) 2013-07-23 2015-09-15 Qualcomm Incorporated Three phase clock recovery delay calibration
US9276731B2 (en) 2013-08-08 2016-03-01 Qualcomm Incorporated N-phase signal transition alignment
US9369237B2 (en) 2013-08-08 2016-06-14 Qualcomm Incorporated Run-length detection and correction
US9215063B2 (en) 2013-10-09 2015-12-15 Qualcomm Incorporated Specifying a 3-phase or N-phase eye pattern
US9246666B2 (en) * 2014-03-27 2016-01-26 Intel Corporation Skew tolerant clock recovery architecture
US9473291B2 (en) * 2014-07-08 2016-10-18 Intel Corporation Apparatuses and methods for reducing switching jitter
US10015027B2 (en) * 2014-10-22 2018-07-03 Micron Technology, Inc. Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures

Also Published As

Publication number Publication date
US9553635B1 (en) 2017-01-24
JP2018525902A (ja) 2018-09-06
WO2017019223A1 (en) 2017-02-02
US20170026083A1 (en) 2017-01-26
CN107852382A (zh) 2018-03-27
EP3326340B1 (en) 2019-11-27
CN107852382B (zh) 2020-11-10
KR20180033190A (ko) 2018-04-02
EP3326340A1 (en) 2018-05-30

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 3A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO ARQUIVAMENTO PUBLICADO NA RPI 2521 DE 30/04/2019.