BR112017010005A2 - aparelho e método para considerar localidade espacial no carregamento de elementos de dados para execução - Google Patents

aparelho e método para considerar localidade espacial no carregamento de elementos de dados para execução

Info

Publication number
BR112017010005A2
BR112017010005A2 BR112017010005A BR112017010005A BR112017010005A2 BR 112017010005 A2 BR112017010005 A2 BR 112017010005A2 BR 112017010005 A BR112017010005 A BR 112017010005A BR 112017010005 A BR112017010005 A BR 112017010005A BR 112017010005 A2 BR112017010005 A2 BR 112017010005A2
Authority
BR
Brazil
Prior art keywords
data elements
loading
execution
processor
spatial locality
Prior art date
Application number
BR112017010005A
Other languages
English (en)
Inventor
Ould-Ahmed-Vall Elmoustapha
Sasanka Ruchira
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112017010005A2 publication Critical patent/BR112017010005A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/283—Plural cache memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

?aparelho e método para considerar localidade espacial no carregamento de elementos de dados para execução? trata-se de, em uma modalidade da invenção, de um processador que compreende um cache de nível superior e pelo menos um núcleo de processador. o pelo menos um núcleo de processador inclui um ou mais registros e uma pluralidade de estágios de processamento de instrução: uma unidade de decodificação para decodificar uma instrução que exige uma entrada de uma pluralidade de elementos de dados, em que um tamanho de cada um dentre a pluralidade de elementos de dados é menor que um tamanho de linha de cache do processador; uma unidade de execução para carregar a pluralidade de elementos de dados no um ou mais registros do processador, sem carregar elementos de dados espacialmente adjacentes à pluralidade de elementos de dados ou à pluralidade de elementos de dados em um cache de nível superior.
BR112017010005A 2014-12-11 2015-10-09 aparelho e método para considerar localidade espacial no carregamento de elementos de dados para execução BR112017010005A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/567,602 US9811464B2 (en) 2014-12-11 2014-12-11 Apparatus and method for considering spatial locality in loading data elements for execution
PCT/US2015/054963 WO2016093943A1 (en) 2014-12-11 2015-10-09 Apparatus and method for considering spatial locality in loading data elements for execution

Publications (1)

Publication Number Publication Date
BR112017010005A2 true BR112017010005A2 (pt) 2018-01-02

Family

ID=56107894

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112017010005A BR112017010005A2 (pt) 2014-12-11 2015-10-09 aparelho e método para considerar localidade espacial no carregamento de elementos de dados para execução

Country Status (9)

Country Link
US (1) US9811464B2 (pt)
EP (1) EP3230852B1 (pt)
JP (1) JP2018502364A (pt)
KR (1) KR102585780B1 (pt)
CN (1) CN107111554B (pt)
BR (1) BR112017010005A2 (pt)
SG (1) SG11201703912VA (pt)
TW (1) TWI622879B (pt)
WO (1) WO2016093943A1 (pt)

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US20170269935A1 (en) * 2011-09-26 2017-09-21 Elmoustapha Ould-Ahmed-Vall Instruction and logic to provide vector loads and stores with strides and masking functionality
US10685290B2 (en) * 2015-12-29 2020-06-16 International Business Machines Corporation Parameter management through RDMA atomic operations
US10262721B2 (en) 2016-03-10 2019-04-16 Micron Technology, Inc. Apparatuses and methods for cache invalidate
US10964869B2 (en) 2017-07-28 2021-03-30 Lg Chem, Ltd. Transparent light emitting element display
US20230089349A1 (en) * 2021-09-21 2023-03-23 Wisconsin Alumni Research Foundation Computer Architecture with Register Name Addressing and Dynamic Load Size Adjustment
CN114356414A (zh) * 2021-12-17 2022-04-15 龙芯中科技术股份有限公司 数据加载方法、装置、电子设备及存储介质

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Also Published As

Publication number Publication date
SG11201703912VA (en) 2017-06-29
CN107111554A (zh) 2017-08-29
EP3230852A4 (en) 2018-07-25
TW201636851A (zh) 2016-10-16
US20160170883A1 (en) 2016-06-16
EP3230852A1 (en) 2017-10-18
EP3230852B1 (en) 2022-12-21
CN107111554B (zh) 2021-01-22
JP2018502364A (ja) 2018-01-25
KR102585780B1 (ko) 2023-10-10
KR20170096101A (ko) 2017-08-23
US9811464B2 (en) 2017-11-07
TWI622879B (zh) 2018-05-01
WO2016093943A1 (en) 2016-06-16

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Legal Events

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B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements