SG11201703912VA - Apparatus and method for considering spatial locality in loading data elements for execution - Google Patents
Apparatus and method for considering spatial locality in loading data elements for executionInfo
- Publication number
- SG11201703912VA SG11201703912VA SG11201703912VA SG11201703912VA SG11201703912VA SG 11201703912V A SG11201703912V A SG 11201703912VA SG 11201703912V A SG11201703912V A SG 11201703912VA SG 11201703912V A SG11201703912V A SG 11201703912VA SG 11201703912V A SG11201703912V A SG 11201703912VA
- Authority
- SG
- Singapore
- Prior art keywords
- execution
- data elements
- loading data
- spatial locality
- considering spatial
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0886—Variable-length word access
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/28—Using a specific disk cache architecture
- G06F2212/283—Plural cache memories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/45—Caching of specific data in cache memory
- G06F2212/452—Instruction code
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/567,602 US9811464B2 (en) | 2014-12-11 | 2014-12-11 | Apparatus and method for considering spatial locality in loading data elements for execution |
| PCT/US2015/054963 WO2016093943A1 (en) | 2014-12-11 | 2015-10-09 | Apparatus and method for considering spatial locality in loading data elements for execution |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11201703912VA true SG11201703912VA (en) | 2017-06-29 |
Family
ID=56107894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11201703912VA SG11201703912VA (en) | 2014-12-11 | 2015-10-09 | Apparatus and method for considering spatial locality in loading data elements for execution |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US9811464B2 (en) |
| EP (1) | EP3230852B1 (en) |
| JP (1) | JP2018502364A (en) |
| KR (1) | KR102585780B1 (en) |
| CN (1) | CN107111554B (en) |
| BR (1) | BR112017010005A2 (en) |
| SG (1) | SG11201703912VA (en) |
| TW (1) | TWI622879B (en) |
| WO (1) | WO2016093943A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170269935A1 (en) * | 2011-09-26 | 2017-09-21 | Elmoustapha Ould-Ahmed-Vall | Instruction and logic to provide vector loads and stores with strides and masking functionality |
| US10685290B2 (en) * | 2015-12-29 | 2020-06-16 | International Business Machines Corporation | Parameter management through RDMA atomic operations |
| US10262721B2 (en) | 2016-03-10 | 2019-04-16 | Micron Technology, Inc. | Apparatuses and methods for cache invalidate |
| US10964869B2 (en) | 2017-07-28 | 2021-03-30 | Lg Chem, Ltd. | Transparent light emitting element display |
| US20230089349A1 (en) * | 2021-09-21 | 2023-03-23 | Wisconsin Alumni Research Foundation | Computer Architecture with Register Name Addressing and Dynamic Load Size Adjustment |
| CN114356414A (en) * | 2021-12-17 | 2022-04-15 | 龙芯中科技术股份有限公司 | Data loading method and device, electronic equipment and storage medium |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0512114A (en) * | 1991-07-04 | 1993-01-22 | Nec Corp | Cache memory |
| US7441110B1 (en) * | 1999-12-10 | 2008-10-21 | International Business Machines Corporation | Prefetching using future branch path information derived from branch prediction |
| US7137111B2 (en) | 2001-11-28 | 2006-11-14 | Sun Microsystems, Inc. | Aggressive prefetch of address chains |
| US6981099B2 (en) * | 2002-12-16 | 2005-12-27 | Sun Microsystems, Inc. | Smart-prefetch |
| US7099999B2 (en) * | 2003-09-30 | 2006-08-29 | International Business Machines Corporation | Apparatus and method for pre-fetching data to cached memory using persistent historical page table data |
| EP1622009A1 (en) * | 2004-07-27 | 2006-02-01 | Texas Instruments Incorporated | JSM architecture and systems |
| US7200717B2 (en) | 2004-10-14 | 2007-04-03 | International Business Machines Corporation | Processor, data processing system and method for synchronizing access to data in shared memory |
| WO2007113757A2 (en) | 2006-04-04 | 2007-10-11 | Koninklijke Philips Electronics N.V. | System and method for supporting a hot-word-first request policy for a multi-heirarchical memory system |
| US7529889B2 (en) * | 2006-08-14 | 2009-05-05 | Arm Limited | Data processing apparatus and method for performing a cache lookup in an energy efficient manner |
| US8285941B2 (en) * | 2008-02-25 | 2012-10-09 | International Business Machines Corporation | Enhancing timeliness of cache prefetching |
| US8171258B2 (en) * | 2009-07-21 | 2012-05-01 | Apple Inc. | Address generation unit with pseudo sum to accelerate load/store operations |
| US8825982B2 (en) | 2010-06-10 | 2014-09-02 | Global Supercomputing Corporation | Storage unsharing |
| US20120254592A1 (en) | 2011-04-01 | 2012-10-04 | Jesus Corbal San Adrian | Systems, apparatuses, and methods for expanding a memory source into a destination register and compressing a source register into a destination memory location |
| US20120254591A1 (en) * | 2011-04-01 | 2012-10-04 | Hughes Christopher J | Systems, apparatuses, and methods for stride pattern gathering of data elements and stride pattern scattering of data elements |
| US20130232304A1 (en) * | 2012-03-05 | 2013-09-05 | Qualcomm Incorporated | Accelerated interleaved memory data transfers in microprocessor-based systems, and related devices, methods, and computer-readable media |
| US9311247B1 (en) * | 2012-03-20 | 2016-04-12 | Marvell International Ltd. | Method and apparatus for detecting patterns of memory accesses in a computing system with out-of-order program execution |
| US8972697B2 (en) * | 2012-06-02 | 2015-03-03 | Intel Corporation | Gather using index array and finite state machine |
| US10049061B2 (en) * | 2012-11-12 | 2018-08-14 | International Business Machines Corporation | Active memory device gather, scatter, and filter |
| US9367466B2 (en) | 2013-02-13 | 2016-06-14 | Advanced Micro Devices, Inc. | Conditional prefetching |
| US9244684B2 (en) * | 2013-03-15 | 2016-01-26 | Intel Corporation | Limited range vector memory access instructions, processors, methods, and systems |
-
2014
- 2014-12-11 US US14/567,602 patent/US9811464B2/en active Active
-
2015
- 2015-10-09 JP JP2017525582A patent/JP2018502364A/en active Pending
- 2015-10-09 EP EP15866639.6A patent/EP3230852B1/en active Active
- 2015-10-09 KR KR1020177012880A patent/KR102585780B1/en active IP Right Grant
- 2015-10-09 BR BR112017010005A patent/BR112017010005A2/en not_active Application Discontinuation
- 2015-10-09 CN CN201580061760.6A patent/CN107111554B/en active Active
- 2015-10-09 WO PCT/US2015/054963 patent/WO2016093943A1/en active Application Filing
- 2015-10-09 SG SG11201703912VA patent/SG11201703912VA/en unknown
- 2015-11-06 TW TW104136669A patent/TWI622879B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| BR112017010005A2 (en) | 2018-01-02 |
| CN107111554A (en) | 2017-08-29 |
| EP3230852A4 (en) | 2018-07-25 |
| TW201636851A (en) | 2016-10-16 |
| US20160170883A1 (en) | 2016-06-16 |
| EP3230852A1 (en) | 2017-10-18 |
| EP3230852B1 (en) | 2022-12-21 |
| CN107111554B (en) | 2021-01-22 |
| JP2018502364A (en) | 2018-01-25 |
| KR102585780B1 (en) | 2023-10-10 |
| KR20170096101A (en) | 2017-08-23 |
| US9811464B2 (en) | 2017-11-07 |
| TWI622879B (en) | 2018-05-01 |
| WO2016093943A1 (en) | 2016-06-16 |
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