BR112016024255A2 - circuitos de detecção de erro de memória cache para detectar inversões de bit em indicadores válidos na memória cache após operações invalidadas, e métodos e sistemas a base de processador relacionados - Google Patents

circuitos de detecção de erro de memória cache para detectar inversões de bit em indicadores válidos na memória cache após operações invalidadas, e métodos e sistemas a base de processador relacionados

Info

Publication number
BR112016024255A2
BR112016024255A2 BR112016024255A BR112016024255A BR112016024255A2 BR 112016024255 A2 BR112016024255 A2 BR 112016024255A2 BR 112016024255 A BR112016024255 A BR 112016024255A BR 112016024255 A BR112016024255 A BR 112016024255A BR 112016024255 A2 BR112016024255 A2 BR 112016024255A2
Authority
BR
Brazil
Prior art keywords
cache
valid
cache memory
invalidated
error detection
Prior art date
Application number
BR112016024255A
Other languages
English (en)
Portuguese (pt)
Inventor
Michael Stempel Brian
Sumner Ingalls John
Philip Speier Thomas
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112016024255A2 publication Critical patent/BR112016024255A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0674—Disk device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
BR112016024255A 2014-04-18 2015-03-30 circuitos de detecção de erro de memória cache para detectar inversões de bit em indicadores válidos na memória cache após operações invalidadas, e métodos e sistemas a base de processador relacionados BR112016024255A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/256,360 US9329930B2 (en) 2014-04-18 2014-04-18 Cache memory error detection circuits for detecting bit flips in valid indicators in cache memory following invalidate operations, and related methods and processor-based systems
PCT/US2015/023269 WO2015160493A1 (en) 2014-04-18 2015-03-30 Cache memory error detection circuits for detecting bit flips in valid indicators in cache memory following invalidate operations, and related methods and processor-based systems

Publications (1)

Publication Number Publication Date
BR112016024255A2 true BR112016024255A2 (pt) 2017-08-15

Family

ID=52823876

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112016024255A BR112016024255A2 (pt) 2014-04-18 2015-03-30 circuitos de detecção de erro de memória cache para detectar inversões de bit em indicadores válidos na memória cache após operações invalidadas, e métodos e sistemas a base de processador relacionados

Country Status (7)

Country Link
US (1) US9329930B2 (https=)
EP (1) EP3132351B1 (https=)
JP (1) JP6339697B2 (https=)
KR (1) KR20160146705A (https=)
CN (1) CN106170774A (https=)
BR (1) BR112016024255A2 (https=)
WO (1) WO2015160493A1 (https=)

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Publication number Priority date Publication date Assignee Title
KR102515417B1 (ko) * 2016-03-02 2023-03-30 한국전자통신연구원 캐시 메모리 장치 및 그것의 동작 방법
WO2021127833A1 (en) * 2019-12-23 2021-07-01 Micron Technology, Inc. Effective avoidance of line cache misses
US11057060B1 (en) * 2020-03-23 2021-07-06 Sage Microelectronics Corporation Method and apparatus for matrix flipping error correction
US11902323B2 (en) * 2021-08-31 2024-02-13 Oracle International Corporation Dynamic cloud workload reallocation based on active security exploits in dynamic random access memory (DRAM)
US11630772B1 (en) * 2021-09-29 2023-04-18 Advanced Micro Devices, Inc. Suppressing cache line modification
US11934265B2 (en) * 2022-02-04 2024-03-19 Apple Inc. Memory error tracking and logging
WO2024158719A1 (en) * 2023-01-26 2024-08-02 Micron Technology, Inc. Preventing back-to-back flips of a bit in bit flipping decoding
TWI877670B (zh) 2023-06-29 2025-03-21 慧榮科技股份有限公司 資料寫入方法與相關記憶體控制器以及資料儲存設備

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JPH06119245A (ja) * 1992-10-01 1994-04-28 Mitsubishi Electric Corp キャッシュメモリ
JPH086854A (ja) * 1993-12-23 1996-01-12 Unisys Corp アウトボードファイルキャッシュ外部処理コンプレックス
US20030131277A1 (en) * 2002-01-09 2003-07-10 Taylor Richard D. Soft error recovery in microprocessor cache memories
US7240277B2 (en) 2003-09-26 2007-07-03 Texas Instruments Incorporated Memory error detection reporting
GB2409301B (en) 2003-12-18 2006-12-06 Advanced Risc Mach Ltd Error correction within a cache memory
JP5008955B2 (ja) * 2006-11-28 2012-08-22 株式会社日立製作所 節電機能を備えたストレージシステム
JP2009059005A (ja) * 2007-08-29 2009-03-19 Panasonic Corp デバッグシステム、デバッグ装置および方法
US7752505B2 (en) 2007-09-13 2010-07-06 International Business Machines Corporation Method and apparatus for detection of data errors in tag arrays
US8291305B2 (en) 2008-09-05 2012-10-16 Freescale Semiconductor, Inc. Error detection schemes for a cache in a data processing system
US8266498B2 (en) 2009-03-31 2012-09-11 Freescale Semiconductor, Inc. Implementation of multiple error detection schemes for a cache
US8924817B2 (en) 2010-09-29 2014-12-30 Advanced Micro Devices, Inc. Method and apparatus for calculating error correction codes for selective data updates
JP2012103826A (ja) 2010-11-09 2012-05-31 Fujitsu Ltd キャッシュメモリシステム
US8775863B2 (en) * 2011-05-31 2014-07-08 Freescale Semiconductor, Inc. Cache locking control
CN103631738B (zh) * 2013-08-15 2016-08-10 中国科学院电子学研究所 一种片外配置和回读fpga装置

Also Published As

Publication number Publication date
JP6339697B2 (ja) 2018-06-06
US9329930B2 (en) 2016-05-03
JP2017511547A (ja) 2017-04-20
EP3132351B1 (en) 2018-03-14
US20150301884A1 (en) 2015-10-22
EP3132351A1 (en) 2017-02-22
KR20160146705A (ko) 2016-12-21
CN106170774A (zh) 2016-11-30
WO2015160493A1 (en) 2015-10-22

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B350 Update of information on the portal [chapter 15.35 patent gazette]