BR112014017659A8 - Determinando acerto/erro de cache de endereços cognominados em cache(s) virtualmente identificado, e sistemas e métodos relacionados - Google Patents

Determinando acerto/erro de cache de endereços cognominados em cache(s) virtualmente identificado, e sistemas e métodos relacionados

Info

Publication number
BR112014017659A8
BR112014017659A8 BR112014017659A BR112014017659A BR112014017659A8 BR 112014017659 A8 BR112014017659 A8 BR 112014017659A8 BR 112014017659 A BR112014017659 A BR 112014017659A BR 112014017659 A BR112014017659 A BR 112014017659A BR 112014017659 A8 BR112014017659 A8 BR 112014017659A8
Authority
BR
Brazil
Prior art keywords
cache
addresses
cache hit
virtual
methods
Prior art date
Application number
BR112014017659A
Other languages
English (en)
Other versions
BR112014017659A2 (pt
Inventor
Norris Dieffenderfer James
d clancy Robert
Philip Speier Thomas
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112014017659A2 publication Critical patent/BR112014017659A2/pt
Publication of BR112014017659A8 publication Critical patent/BR112014017659A8/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Abstract

DETERMINAÇÃO DE ACERTO/ERRO EM CACHE DE ENDEREÇOS DE ALIASING EM CACHE(S) VIRTUALMENTE IDENTIFICADA(S), E SISTEMAS E MÉTODOS RELACIONADOS. São revelados aparelhos e sistemas e métodos relacionados para determinar acerto/erro em cache de Endereços de aliasing em cache(s) virtualmente identificada(s). Em uma modalidade, é provido um detector de acerto/erro em cache com aliasing virtual para uma cache VIVT. O detector compreende um TLB configurado para receber um primeiro endereço virtual e um segundo endereço virtual a partir da cache VIVT resultando de uma leitura indexada para a cache VIVT com base no primeiro endereço virtual. O TLB é configurado adicionalmente para gerar o prime iro e o segundo endereço físico convertido a partir do primeiro e segundo endereço virtual, respectivamente. O detector compreende ainda um comparador configurado para receber o primeiro e o segundo endereço físico e efetuar uma geração de um indicador de acerto/erro em cache com aliasing com base em uma comparação do primeiro e do segundo endereço físico. Dessa maneira, o detector de acerto/erro em cache com aliasing virtual gera corretamente acertos em cache e erros em cache, mesmo na presença de endereçamento com aliasing.
BR112014017659A 2012-01-18 2013-01-17 Determinando acerto/erro de cache de endereços cognominados em cache(s) virtualmente identificado, e sistemas e métodos relacionados BR112014017659A8 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261587756P 2012-01-18 2012-01-18
US13/478,149 US9110830B2 (en) 2012-01-18 2012-05-23 Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods
PCT/US2013/021849 WO2013109696A2 (en) 2012-01-18 2013-01-17 Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods

Publications (2)

Publication Number Publication Date
BR112014017659A2 BR112014017659A2 (pt) 2017-06-20
BR112014017659A8 true BR112014017659A8 (pt) 2017-07-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
BR112014017659A BR112014017659A8 (pt) 2012-01-18 2013-01-17 Determinando acerto/erro de cache de endereços cognominados em cache(s) virtualmente identificado, e sistemas e métodos relacionados

Country Status (9)

Country Link
US (1) US9110830B2 (pt)
EP (1) EP2805245B1 (pt)
JP (1) JP6019136B2 (pt)
KR (1) KR101570155B1 (pt)
CN (1) CN104040509B (pt)
BR (1) BR112014017659A8 (pt)
IN (1) IN2014CN04649A (pt)
TW (1) TWI502349B (pt)
WO (1) WO2013109696A2 (pt)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013097671A (ja) * 2011-11-02 2013-05-20 Fujitsu Ltd アドレス変換装置、アドレス変換装置の制御方法及び演算処理装置
KR20160079051A (ko) * 2013-12-27 2016-07-05 인텔 코포레이션 이중 전압 비대칭 메모리 셀
CN104375963B (zh) 2014-11-28 2019-03-15 上海兆芯集成电路有限公司 基于缓存一致性的控制系统和方法
WO2016097795A1 (en) 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or subset or tis ways depending on mode
WO2016097808A1 (en) 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Dynamic cache replacement way selection based on address tag bits
KR101820223B1 (ko) 2014-12-14 2018-01-18 비아 얼라이언스 세미컨덕터 씨오., 엘티디. 모드에 따라 선택적으로 하나 또는 복수의 셋트를 선택하도록 동적으로 구성가능한 멀티 모드 셋트 연관 캐시 메모리
US9934152B1 (en) * 2015-02-17 2018-04-03 Marvell International Ltd. Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cache
CN106155937B (zh) * 2015-04-07 2019-03-05 龙芯中科技术有限公司 缓存访问方法、设备和处理器
US10121220B2 (en) * 2015-04-28 2018-11-06 Nvidia Corporation System and method for creating aliased mappings to minimize impact of cache invalidation
US20160378684A1 (en) 2015-06-26 2016-12-29 Intel Corporation Multi-page check hints for selective checking of protected container page versus regular page type indications for pages of convertible memory
CN105095113B (zh) * 2015-07-21 2018-06-29 浪潮(北京)电子信息产业有限公司 一种缓存管理方法和系统
US9626300B2 (en) * 2015-07-27 2017-04-18 Google Inc. Address caching in switches
GB2543745B (en) * 2015-10-15 2018-07-04 Advanced Risc Mach Ltd An apparatus and method for operating a virtually indexed physically tagged cache
US10042777B2 (en) * 2016-03-30 2018-08-07 Qualcomm Incorporated Hardware-based translation lookaside buffer (TLB) invalidation
US9772943B1 (en) * 2016-04-01 2017-09-26 Cavium, Inc. Managing synonyms in virtual-address caches
US10067870B2 (en) 2016-04-01 2018-09-04 Intel Corporation Apparatus and method for low-overhead synchronous page table updates
US10120814B2 (en) * 2016-04-01 2018-11-06 Intel Corporation Apparatus and method for lazy translation lookaside buffer (TLB) coherence
US20180089094A1 (en) * 2016-09-23 2018-03-29 Qualcomm Incorporated Precise invalidation of virtually tagged caches
US10061698B2 (en) * 2017-01-31 2018-08-28 Qualcomm Incorporated Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur
US10318436B2 (en) 2017-07-25 2019-06-11 Qualcomm Incorporated Precise invalidation of virtually tagged caches
JP7242634B2 (ja) * 2017-07-30 2023-03-20 ニューロブレード リミテッド メモリチップ
US10725782B2 (en) * 2017-09-12 2020-07-28 Qualcomm Incorporated Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
KR102151180B1 (ko) * 2017-11-20 2020-09-02 삼성전자주식회사 효율적인 가상 캐시 구현을 위한 시스템 및 방법
US10545879B2 (en) * 2018-03-26 2020-01-28 Arm Limited Apparatus and method for handling access requests
US10846235B2 (en) * 2018-04-28 2020-11-24 International Business Machines Corporation Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator
US10489305B1 (en) 2018-08-14 2019-11-26 Texas Instruments Incorporated Prefetch kill and revival in an instruction cache
CN109144901B (zh) * 2018-10-10 2024-01-02 古进 公式化虚拟地址转换
US10977175B2 (en) * 2019-02-01 2021-04-13 International Business Machines Corporation Virtual cache tag renaming for synonym handling
US11169930B2 (en) * 2019-05-28 2021-11-09 Micron Technology, Inc. Fine grain data migration to or from borrowed memory
US11061819B2 (en) 2019-05-28 2021-07-13 Micron Technology, Inc. Distributed computing based on memory as a service

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02208756A (ja) * 1989-02-09 1990-08-20 Nec Corp キャッシュメモリ制御方式
JPH07287668A (ja) * 1994-04-19 1995-10-31 Hitachi Ltd データ処理装置
US6175906B1 (en) * 1996-12-06 2001-01-16 Advanced Micro Devices, Inc. Mechanism for fast revalidation of virtual tags
US6298411B1 (en) * 1999-01-05 2001-10-02 Compaq Computer Corporation Method and apparatus to share instruction images in a virtual cache
US8417915B2 (en) 2005-08-05 2013-04-09 Arm Limited Alias management within a virtually indexed and physically tagged cache memory
WO2007094046A1 (ja) 2006-02-14 2007-08-23 Fujitsu Limited コヒーレンシ維持装置およびコヒーレンシ維持方法
US7802055B2 (en) * 2006-04-19 2010-09-21 Qualcomm Incorporated Virtually-tagged instruction cache with physically-tagged behavior
JP4783229B2 (ja) 2006-07-19 2011-09-28 パナソニック株式会社 キャッシュメモリシステム
US7991963B2 (en) * 2007-12-31 2011-08-02 Intel Corporation In-memory, in-page directory cache coherency scheme
US8041894B2 (en) 2008-02-25 2011-10-18 International Business Machines Corporation Method and system for a multi-level virtual/real cache system with synonym resolution
US8090984B2 (en) * 2008-12-10 2012-01-03 Freescale Semiconductor, Inc. Error detection and communication of an error location in multi-processor data processing system having processors operating in Lockstep
US20110145542A1 (en) * 2009-12-15 2011-06-16 Qualcomm Incorporated Apparatuses, Systems, and Methods for Reducing Translation Lookaside Buffer (TLB) Lookups
JP2011198091A (ja) 2010-03-19 2011-10-06 Toshiba Corp 仮想アドレスキャッシュメモリ、プロセッサ及びマルチプロセッサシステム
KR20120083160A (ko) * 2011-01-17 2012-07-25 삼성전자주식회사 메모리 관리 유닛, 이를 포함하는 장치들, 및 이의 동작 방법
US8972642B2 (en) * 2011-10-04 2015-03-03 Qualcomm Incorporated Low latency two-level interrupt controller interface to multi-threaded processor
JP2013097671A (ja) * 2011-11-02 2013-05-20 Fujitsu Ltd アドレス変換装置、アドレス変換装置の制御方法及び演算処理装置

Also Published As

Publication number Publication date
US9110830B2 (en) 2015-08-18
KR101570155B1 (ko) 2015-11-19
WO2013109696A3 (en) 2013-10-03
CN104040509B (zh) 2018-01-30
US20130185520A1 (en) 2013-07-18
EP2805245A2 (en) 2014-11-26
IN2014CN04649A (pt) 2015-09-18
TWI502349B (zh) 2015-10-01
BR112014017659A2 (pt) 2017-06-20
KR20140116935A (ko) 2014-10-06
JP2015507810A (ja) 2015-03-12
EP2805245B1 (en) 2019-10-09
WO2013109696A2 (en) 2013-07-25
TW201346557A (zh) 2013-11-16
JP6019136B2 (ja) 2016-11-02
CN104040509A (zh) 2014-09-10

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B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

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B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2549 DE 12-11-2019 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.