BR112015030433A2 - direção de interrupção gerenciada por sistema operacional em sistemas de processador múltiplo - Google Patents

direção de interrupção gerenciada por sistema operacional em sistemas de processador múltiplo

Info

Publication number
BR112015030433A2
BR112015030433A2 BR112015030433A BR112015030433A BR112015030433A2 BR 112015030433 A2 BR112015030433 A2 BR 112015030433A2 BR 112015030433 A BR112015030433 A BR 112015030433A BR 112015030433 A BR112015030433 A BR 112015030433A BR 112015030433 A2 BR112015030433 A2 BR 112015030433A2
Authority
BR
Brazil
Prior art keywords
processor
interrupt
load
operating system
given
Prior art date
Application number
BR112015030433A
Other languages
English (en)
Other versions
BR112015030433B1 (pt
BR112015030433A8 (pt
Inventor
Raffman Andrew
Wohlgemuth Jason
Kim Minsang
Fatemieh Omid
Brown Tristan
Barakat Youssef
Original Assignee
Microsoft Technology Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Technology Licensing Llc filed Critical Microsoft Technology Licensing Llc
Publication of BR112015030433A2 publication Critical patent/BR112015030433A2/pt
Publication of BR112015030433A8 publication Critical patent/BR112015030433A8/pt
Publication of BR112015030433B1 publication Critical patent/BR112015030433B1/pt

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3003Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3419Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3433Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment for load management
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5083Techniques for rebalancing the load in a distributed system
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/835Timestamp
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/865Monitoring of software
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)

Abstract

resumo patente de invenção: "direção de interrupção gerenciada por sistema operacional em sistemas de processador múltiplo". a presente invenção refere-se a um sistema operacional que é provido, no qual um roteador de interrupção dirige dinamicamente cada interrupção para um ou mais processadores em um conjunto de processadores, com base em uma informação de carga geral a partir do conjunto de processadores. uma fonte de interrupção é atribuída a um processador com base na carga imposta pela fonte de interrupção e na carga geral alvo para o processador. por exemplo, cada processador pode manter uma informação sobre cada interrupção que ele processa ao longo do tempo. o sistema operacional recebe sua informação de carga histórica para determinar uma carga esperada para interrupções de um dado tipo a partir de um dado dispositivo, uma carga geral no sistema e uma carga alvo para cada processador. dado um conjunto de fontes de interrupção, suas cargas esperadas e uma carga alvo para cada processador, cada fonte de interrupção pode ser atribuída dinamicamente a um processador durante um tempo de rodada do sistema. em uma base regular, estas atribuições podem ser mudadas, dadas as condições de operação atuais do sistema.
BR112015030433-8A 2013-06-13 2013-09-18 Processo executado por um computador que inclui uma pluralidade de processadores, artigo de fabricação e computador BR112015030433B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/917,634 US9424212B2 (en) 2013-06-13 2013-06-13 Operating system-managed interrupt steering in multiprocessor systems
US13/917,634 2013-06-13
PCT/US2013/060243 WO2014200521A1 (en) 2013-06-13 2013-09-18 Operating system-managed interrupt steering in multiprocessor systems

Publications (3)

Publication Number Publication Date
BR112015030433A2 true BR112015030433A2 (pt) 2017-07-25
BR112015030433A8 BR112015030433A8 (pt) 2019-12-24
BR112015030433B1 BR112015030433B1 (pt) 2022-05-17

Family

ID=49382570

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015030433-8A BR112015030433B1 (pt) 2013-06-13 2013-09-18 Processo executado por um computador que inclui uma pluralidade de processadores, artigo de fabricação e computador

Country Status (5)

Country Link
US (2) US9424212B2 (pt)
EP (1) EP3008595A1 (pt)
CN (1) CN105378668B (pt)
BR (1) BR112015030433B1 (pt)
WO (1) WO2014200521A1 (pt)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013095337A1 (en) * 2011-12-19 2013-06-27 Intel Corporation A system and deterministic method for servicing msi interrupts using direct cache access
CN104169879B (zh) * 2012-04-24 2019-01-04 英特尔公司 用于动态中断重新配置的方法和计算机系统
US9424212B2 (en) * 2013-06-13 2016-08-23 Microsoft Technology Licensing, Llc Operating system-managed interrupt steering in multiprocessor systems
US9779468B2 (en) 2015-08-03 2017-10-03 Apple Inc. Method for chaining media processing
US10585826B2 (en) * 2016-01-25 2020-03-10 Advanced Micro Devices, Inc. Using processor types for processing interrupts in a computing device
CN112347013A (zh) * 2016-04-27 2021-02-09 华为技术有限公司 一种中断处理方法以及相关装置
US10353766B2 (en) * 2016-09-09 2019-07-16 International Business Machines Corporation Managing execution of computer tasks under time constraints
CN112650616A (zh) * 2021-01-05 2021-04-13 上海擎昆信息科技有限公司 一种中断检测方法、装置和系统
CN114546911A (zh) * 2022-01-12 2022-05-27 阿里巴巴(中国)有限公司 中断处理方法和装置、电子设备及计算机可读存储介质

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993000638A1 (en) * 1991-06-26 1993-01-07 Ast Research, Inc. Automatic distribution of interrupts controller for a multiple processor computer system
JP3008896B2 (ja) * 1997-06-16 2000-02-14 日本電気株式会社 共有バス型マルチプロセッサシステムの割り込み負荷分散システム
US5944840A (en) * 1997-09-10 1999-08-31 Bluewater Systems, Inc. Continuous monitor for interrupt latency in real time systems
US6604136B1 (en) * 1998-06-27 2003-08-05 Intel Corporation Application programming interfaces and methods enabling a host to interface with a network processor
US6986066B2 (en) 2001-01-05 2006-01-10 International Business Machines Corporation Computer system having low energy consumption
US6813665B2 (en) * 2001-09-21 2004-11-02 Intel Corporation Interrupt method, system and medium
US7328294B2 (en) * 2001-12-03 2008-02-05 Sun Microsystems, Inc. Methods and apparatus for distributing interrupts
US7444639B2 (en) * 2001-12-20 2008-10-28 Texas Insturments Incorporated Load balanced interrupt handling in an embedded symmetric multiprocessor system
US7028302B2 (en) * 2002-04-24 2006-04-11 Hewlett-Packard Development Company, L.P. System and method for automatically tuning a multiprocessor computer system
US7191349B2 (en) * 2002-12-26 2007-03-13 Intel Corporation Mechanism for processor power state aware distribution of lowest priority interrupt
US20050125582A1 (en) * 2003-12-08 2005-06-09 Tu Steven J. Methods and apparatus to dispatch interrupts in multi-processor systems
US20060123422A1 (en) 2004-12-02 2006-06-08 International Business Machines Corporation Processor packing in an SMP server to conserve energy
US20070005742A1 (en) 2005-06-30 2007-01-04 Avigdor Eldar Efficient network communications via directed processor interrupts
US7581052B1 (en) 2005-08-22 2009-08-25 Sun Microsystems, Inc. Approach for distributing multiple interrupts among multiple processors
US7610425B2 (en) * 2005-08-22 2009-10-27 Sun Microsystems, Inc. Approach for managing interrupt load distribution
US7694055B2 (en) * 2005-10-15 2010-04-06 International Business Machines Corporation Directing interrupts to currently idle processors
US9032127B2 (en) * 2006-09-14 2015-05-12 Hewlett-Packard Development Company, L.P. Method of balancing I/O device interrupt service loading in a computer system
JP2008176360A (ja) * 2007-01-16 2008-07-31 Renesas Technology Corp マルチプロセッサシステム
US8032681B2 (en) * 2007-09-06 2011-10-04 Intel Corporation Processor selection for an interrupt based on willingness to accept the interrupt and on priority
US7962679B2 (en) * 2007-09-28 2011-06-14 Intel Corporation Interrupt balancing for multi-core and power
US7962771B2 (en) 2007-12-31 2011-06-14 Intel Corporation Method, system, and apparatus for rerouting interrupts in a multi-core processor
CN101354664B (zh) * 2008-08-19 2011-12-28 中兴通讯股份有限公司 多核处理器中断负载均衡方法和装置
JP2010055296A (ja) 2008-08-27 2010-03-11 Fujitsu Ltd 負荷分散プログラム及び負荷分散装置
US8260996B2 (en) * 2009-04-24 2012-09-04 Empire Technology Development Llc Interrupt optimization for multiprocessors
US8321614B2 (en) 2009-04-24 2012-11-27 Empire Technology Development Llc Dynamic scheduling interrupt controller for multiprocessors
TWI497419B (zh) * 2011-10-20 2015-08-21 Via Tech Inc 電腦裝置及其中斷任務分配方法
KR20130049110A (ko) 2011-11-03 2013-05-13 삼성전자주식회사 인터럽트 할당 방법 및 장치
US9424212B2 (en) * 2013-06-13 2016-08-23 Microsoft Technology Licensing, Llc Operating system-managed interrupt steering in multiprocessor systems

Also Published As

Publication number Publication date
US20140372649A1 (en) 2014-12-18
BR112015030433B1 (pt) 2022-05-17
CN105378668B (zh) 2019-05-31
CN105378668A (zh) 2016-03-02
WO2014200521A1 (en) 2014-12-18
EP3008595A1 (en) 2016-04-20
US9424212B2 (en) 2016-08-23
US10157155B2 (en) 2018-12-18
BR112015030433A8 (pt) 2019-12-24
US20160357689A1 (en) 2016-12-08

Similar Documents

Publication Publication Date Title
BR112015030433A2 (pt) direção de interrupção gerenciada por sistema operacional em sistemas de processador múltiplo
BR112015027149A2 (pt) sistema gerador de aerossol que compreende uma fonte de composto de melhoramento de distribuição e uma fonte de medicamento
BR112018015135A2 (pt) sistema de análise de indústria baseado em clima
BR112018002040A2 (pt) controle de uma nuvem de dispositivo
BR112015031288A2 (pt) fluido de trabalho para ciclo térmico, composição para sistema de ciclo térmico e sistema de ciclo térmico
BR112014016099A8 (pt) método e sistema de topologia de borda de nuvem
BR112013004722A2 (pt) "computação cspf retransmitida para múltiplas áreas e múltiplos sistemas autônomos."
BR112015031238A2 (pt) painel de construção com um sistema de travamento mecânico
BR112015027830A2 (pt) método e sistema de identificação de biomarcador
BR112016020103A8 (pt) computação de programações de longo prazo para transferências de dados por uma rede de área ampla
BR112013006586A2 (pt) sistema que inclui um controlador multimídia programável, método para ganhar acesso, por um usuáro, ao controle de um controlador multimídia programável, método de operação de um sistema controlador multimídia programável, e, sistema controlador multimídia programável
BR112014030344A2 (pt) lembretes de ciência de localização
BR112015019943A2 (pt) tecnologia de centro de dados distribuído
BR112015012051A2 (pt) composições e métodos para modulação de expressão de fgfr3
BR112014021507A2 (pt) Método e aparelho para compartilhar informação, e dispositivo de computador
BR112015001647A2 (pt) método para associar um elemento óptico com pelo menos uma fonte de luz; elemento óptico ativo; aparelho de iluminação que inclui uma memória e um controlador que pode ser operado para executar as instruções armazenadas na memória; e sistema de iluminação
BR112015020693A8 (pt) método e sistema de computação para provisionar um volume que possui múltiplas camadas correspondendo a diferentes conjuntos de atributos
BR112014010182A2 (pt) comutação entre contextos operacionais
BR112019001748A2 (pt) sistema de gestão de fila utilizando provedores de serviços virtuais
BR112014032625A2 (pt) sistema de computador; processador de computador; e compilador
BR112014007889A2 (pt) método, dispositivo, sistema, e, programa
BR112014004453A2 (pt) regulagens de energia para sistemas de transporte
BR112017010075A2 (pt) processadores, métodos, sistemas e instruções de ajuste de coordenada de morton
BR112015030435A2 (pt) temporizadores por processador virtuais para sistemas de processador múltiplo
BR112014013811A8 (pt) sistema mecânico que compreende uma peça de desgaste e um suporte, e balde que compreende pelo menos tal sistema mecânico

Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 18/09/2013, OBSERVADAS AS CONDICOES LEGAIS