BR112015018321A2 - gerenciamento dinâmico de memória heterogênea - Google Patents

gerenciamento dinâmico de memória heterogênea

Info

Publication number
BR112015018321A2
BR112015018321A2 BR112015018321A BR112015018321A BR112015018321A2 BR 112015018321 A2 BR112015018321 A2 BR 112015018321A2 BR 112015018321 A BR112015018321 A BR 112015018321A BR 112015018321 A BR112015018321 A BR 112015018321A BR 112015018321 A2 BR112015018321 A2 BR 112015018321A2
Authority
BR
Brazil
Prior art keywords
memory
computing device
soc
type
dram
Prior art date
Application number
BR112015018321A
Other languages
English (en)
Inventor
Bond Barry
Lee Brian
Tremblay Marc
John Ramberg Mark
Sadovsky Vlad
Original Assignee
Microsoft Technology Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Technology Licensing Llc filed Critical Microsoft Technology Licensing Llc
Publication of BR112015018321A2 publication Critical patent/BR112015018321A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/501—Performance criteria
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Power Sources (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Debugging And Monitoring (AREA)
  • Dram (AREA)

Abstract

resumo patente de invenção: "gerenciamento dinâmico de memória heterogênea". a presente invenção refere-se a um método para operar um dispositivo de computação que inclui gerenciar dinamicamente pelo menos dois tipos de memória baseado em cargas de trabalho, ou solicitações de diferentes tipos de aplicações. um primeiro tipo de memória pode ser uma memória de alto desempenho que pode ter uma largura de banda mais alta, latência de memória mais baixa e/ou consumo de energia mais baixo do que um segundo tipo de memória no dispositivo de computação. em uma modalidade, o dispositivo de computação inclui sistema sobre um chip (soc) que inclui wide i/o dram posicionadas com um ou mais núcleos de processador. uma memória de acesso randômico dinâmica baixa energia dupla taxa de dados 3 (lpddr3 dram) está externamente conectada no soc ou é uma parte embutida do soc. em modalidades, o dispositivo de computação pode estar incluído em pelo menos um telefone celular, dispositivo móvel, sistema embutido, videogame, console de mídia, computador laptop, computador desktop, servidor e/ou centro de dados. 1/1
BR112015018321A 2013-02-04 2014-01-29 gerenciamento dinâmico de memória heterogênea BR112015018321A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/758,613 US9110592B2 (en) 2013-02-04 2013-02-04 Dynamic allocation of heterogenous memory in a computing system
PCT/US2014/013468 WO2014120698A1 (en) 2013-02-04 2014-01-29 Dynamic management of heterogeneous memory

Publications (1)

Publication Number Publication Date
BR112015018321A2 true BR112015018321A2 (pt) 2017-07-18

Family

ID=50156901

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015018321A BR112015018321A2 (pt) 2013-02-04 2014-01-29 gerenciamento dinâmico de memória heterogênea

Country Status (11)

Country Link
US (1) US9110592B2 (pt)
EP (1) EP2951689A1 (pt)
JP (1) JP2016510471A (pt)
KR (1) KR102207598B1 (pt)
CN (1) CN105144106B (pt)
AU (1) AU2014212559A1 (pt)
BR (1) BR112015018321A2 (pt)
CA (1) CA2898127A1 (pt)
MX (1) MX352450B (pt)
RU (1) RU2015132229A (pt)
WO (1) WO2014120698A1 (pt)

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Also Published As

Publication number Publication date
MX352450B (es) 2017-11-24
EP2951689A1 (en) 2015-12-09
AU2014212559A1 (en) 2015-07-30
US20140223098A1 (en) 2014-08-07
MX2015010046A (es) 2016-03-04
RU2015132229A (ru) 2017-02-08
CN105144106A (zh) 2015-12-09
CN105144106B (zh) 2020-05-05
KR20150114958A (ko) 2015-10-13
CA2898127A1 (en) 2014-08-07
US9110592B2 (en) 2015-08-18
KR102207598B1 (ko) 2021-01-25
JP2016510471A (ja) 2016-04-07
WO2014120698A1 (en) 2014-08-07

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