BE902870A - Procede d'interconnexion de microprocesseurs - Google Patents

Procede d'interconnexion de microprocesseurs

Info

Publication number
BE902870A
BE902870A BE0/215333A BE215333A BE902870A BE 902870 A BE902870 A BE 902870A BE 0/215333 A BE0/215333 A BE 0/215333A BE 215333 A BE215333 A BE 215333A BE 902870 A BE902870 A BE 902870A
Authority
BE
Belgium
Prior art keywords
slave
character
microprocessors
register
intended
Prior art date
Application number
BE0/215333A
Other languages
English (en)
French (fr)
Original Assignee
Sagem
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sagem filed Critical Sagem
Publication of BE902870A publication Critical patent/BE902870A/fr

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/17Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
BE0/215333A 1984-07-17 1985-07-12 Procede d'interconnexion de microprocesseurs BE902870A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8411285A FR2568035B1 (fr) 1984-07-17 1984-07-17 Procede d'interconnexion de microprocesseurs

Publications (1)

Publication Number Publication Date
BE902870A true BE902870A (fr) 1985-11-04

Family

ID=9306186

Family Applications (1)

Application Number Title Priority Date Filing Date
BE0/215333A BE902870A (fr) 1984-07-17 1985-07-12 Procede d'interconnexion de microprocesseurs

Country Status (9)

Country Link
US (1) US4827398A (enExample)
JP (1) JPS6136860A (enExample)
AU (1) AU582372B2 (enExample)
BE (1) BE902870A (enExample)
DE (1) DE3525046A1 (enExample)
FR (1) FR2568035B1 (enExample)
IN (1) IN164434B (enExample)
IT (1) IT1199894B (enExample)
YU (1) YU45921B (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3751609T2 (de) * 1986-09-01 1996-07-04 Nippon Electric Co Datenprozessor mit Hochgeschwindigkeitsdatenübertragung.
DE3789743T2 (de) * 1986-09-01 1994-08-18 Nippon Electric Co Serielles Datenübertragungssystem.
DE3643944C2 (de) * 1986-12-22 1997-03-20 Vdo Schindling System zum Austausch von Informationen zwischen einem ersten und einem zweiten Mikroprozessor
JPH0786855B2 (ja) * 1987-04-15 1995-09-20 日本電気株式会社 シリアルデ−タ処理装置
FR2654372B1 (fr) * 1989-11-16 1992-01-17 Siderurgie Fse Inst Rech Cylindre pour un dispositif de coulee continue sur un ou entre deux cylindres.
JP2508328B2 (ja) * 1989-12-20 1996-06-19 日本電気株式会社 多機能電話機のサ―ビス機能起動方式
DE3942139C2 (de) * 1989-12-20 1995-04-13 Siemens Ag Verfahren zur Initialisierung von in einem Rechnersystem zusammengeschalteten Prozessoren
IT1239596B (it) * 1990-02-16 1993-11-10 Sincon Spa Sistemi Imformativi Rete di collegamento per la gestione di dati in elaborazioni parallele.
JPH0816739A (ja) * 1994-06-24 1996-01-19 Tokimec Inc リーダライタとデータキャリアを用いたデータ処理装置
IES65387B2 (en) * 1995-03-24 1995-10-18 Lake Res Ltd Communication apparatus for communicating two microprocessors

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699529A (en) * 1971-01-07 1972-10-17 Rca Corp Communication among computers
GB1474385A (en) * 1973-12-14 1977-05-25 Int Computers Ltd Multiprocessor data processing systems
AT335779B (de) * 1974-10-04 1977-03-25 Schrack Elektrizitaets Ag E Schaltungsanordnung zur steuernden taktweisen ubertragung von daten uber einen oder mehrere speicher zu einer datenverarbeitungsanlage
DE2546202A1 (de) * 1975-10-15 1977-04-28 Siemens Ag Rechnersystem aus mehreren miteinander verbundenen und zusammenwirkenden einzelrechnern und verfahren zum betrieb des rechnersystems
US4368512A (en) * 1978-06-30 1983-01-11 Motorola, Inc. Advanced data link controller having a plurality of multi-bit status registers
AT361726B (de) * 1979-02-19 1981-03-25 Philips Nv Datenverarbeitungsanlage mit mindestens zwei mikrocomputern
JPS6019821B2 (ja) * 1979-10-17 1985-05-18 株式会社リコー シリアルデ−タ受信方式
US4365294A (en) * 1980-04-10 1982-12-21 Nizdorf Computer Corporation Modular terminal system using a common bus
FR2490435B1 (fr) * 1980-09-16 1988-03-18 Cii Honeywell Bull Dispositif pour la transmission de signaux asynchrones entre plusieurs unites d'un systeme de traitement de l'information reliees par une ligne de transmission
JPS57117027A (en) * 1981-01-13 1982-07-21 Nec Corp Signal sending and receiving circuit
US4456956A (en) * 1981-08-24 1984-06-26 Data General Corp. Method and apparatus for controlling access of a network transmission bus between a plurality of spaced apart computer stations
US4449202A (en) * 1981-12-04 1984-05-15 Ncr Corporation Full duplex integrated circuit communication controller
US4484273A (en) * 1982-09-03 1984-11-20 Sequoia Systems, Inc. Modular computer system

Also Published As

Publication number Publication date
YU117585A (en) 1988-02-29
IN164434B (enExample) 1989-03-18
DE3525046C2 (enExample) 1991-05-16
FR2568035A1 (fr) 1986-01-24
YU45921B (sh) 1992-09-07
FR2568035B1 (fr) 1989-06-02
IT1199894B (it) 1989-01-05
US4827398A (en) 1989-05-02
DE3525046A1 (de) 1986-01-30
AU4506785A (en) 1986-01-23
JPS6136860A (ja) 1986-02-21
AU582372B2 (en) 1989-03-23
IT8567652A0 (it) 1985-07-16

Similar Documents

Publication Publication Date Title
BE902870A (fr) Procede d'interconnexion de microprocesseurs
Endrizzi et al. Genetics, cytology, and evolution of Gossypium
IT8819722A0 (it) Metodo migliorato per l'analisi di acidi nucleici, una combinazione di reagenti e un kit per eseguirlo.
EP0352103A3 (en) Pipeline bubble compression in a computer system
DE19681660T1 (de) Verfahren zum Ausführen von Operationen an verschiedenen Datenarten, das für verschiedene Betriebssystemtechniken unsichtbar ist
DE60126967D1 (de) Verfahren und Vorrichtung für Anti-Aliasing durch Überabtastung
WO2001033332A3 (en) Method and apparatus for representing arithmetic intervals within a computer system
EP0395348A3 (en) Method and apparatus for multi-gauge computation
EP0680185A3 (en) A distributed computer system
EP0747859A3 (en) Interrupt scheme for updating a local memory
BR0012828A (pt) Método e sistema modulares para executar consulta de banco de dados
EP0838772A3 (en) Method and apparatus for design verification using emulation and simulation
DE3853336D1 (de) Rechnergraphikgerät zur Verarbeitung von Beleuchtungsmodellinformation.
DE3883733D1 (de) Bedienungsverfahren eines elektronischen Datenverarbeitungssystems zum Dokumententransfer zwischen Endbenutzern.
RU94033149A (ru) Селективный ограничительный фрагмент амплификации: общий метод для днк "фингерпринтинга"
DE3856313D1 (de) Anpassungsprogramm zum Datenaustausch zwischen Objekten in einem objektbasierten Datenverarbeitungssystem
EP0899654A3 (en) A data processing system and method
DE3851207D1 (de) Verfahren zur Bedienung eines Rechnergraphiksystems.
EP0860780A3 (en) Bus control system in a multi-processor system
DE3751083D1 (de) Schnittstelle für seriellen Bus, fähig für den Datentransfer in verschiedenen Formaten.
EP0359233A3 (en) Computer system and method for changing operation speed of system bus
EP0350713A3 (en) Bit map search by competitive processors
DE68914289D1 (de) Busschnittstellensteuerung für rechnergrafiken.
EP0280821A3 (en) Interface between processor and special instruction processor in digital data processing system
EP0318702A3 (en) Data processor with direct data transfer between coprocessor and memory

Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: SOC. D'APPLICATIONS GENERALES D'ELECTRICITE ET DE

Effective date: 19940731