BE855162A - Procede pour former des connexions au travers d'une couche isolante dans la fabrication de circuits integres - Google Patents

Procede pour former des connexions au travers d'une couche isolante dans la fabrication de circuits integres

Info

Publication number
BE855162A
BE855162A BE178015A BE178015A BE855162A BE 855162 A BE855162 A BE 855162A BE 178015 A BE178015 A BE 178015A BE 178015 A BE178015 A BE 178015A BE 855162 A BE855162 A BE 855162A
Authority
BE
Belgium
Prior art keywords
manufacture
insulating layer
integrated circuits
forming connections
connections
Prior art date
Application number
BE178015A
Other languages
English (en)
French (fr)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BE855162A publication Critical patent/BE855162A/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/143—Masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4076—Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/15—Silicon on sapphire SOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
BE178015A 1976-06-30 1977-05-27 Procede pour former des connexions au travers d'une couche isolante dans la fabrication de circuits integres BE855162A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/701,451 US4076575A (en) 1976-06-30 1976-06-30 Integrated fabrication method of forming connectors through insulative layers

Publications (1)

Publication Number Publication Date
BE855162A true BE855162A (fr) 1977-09-16

Family

ID=24817435

Family Applications (1)

Application Number Title Priority Date Filing Date
BE178015A BE855162A (fr) 1976-06-30 1977-05-27 Procede pour former des connexions au travers d'une couche isolante dans la fabrication de circuits integres

Country Status (10)

Country Link
US (1) US4076575A (xx)
JP (1) JPS533172A (xx)
BE (1) BE855162A (xx)
BR (1) BR7704314A (xx)
CA (1) CA1082370A (xx)
CH (1) CH614562A5 (xx)
DE (1) DE2729030C2 (xx)
FR (1) FR2357071A1 (xx)
IT (1) IT1115667B (xx)
NL (1) NL7706108A (xx)

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US4059069A (en) * 1976-08-30 1977-11-22 The Arnold Engineering Company Coating apparatus
US4172004A (en) * 1977-10-20 1979-10-23 International Business Machines Corporation Method for forming dense dry etched multi-level metallurgy with non-overlapped vias
US4289834A (en) * 1977-10-20 1981-09-15 Ibm Corporation Dense dry etched multi-level metallurgy with non-overlapped vias
US4176029A (en) * 1978-03-02 1979-11-27 Sperry Rand Corporation Subminiature bore and conductor formation
US4263603A (en) * 1978-03-02 1981-04-21 Sperry Corporation Subminiature bore and conductor formation
US4184909A (en) * 1978-08-21 1980-01-22 International Business Machines Corporation Method of forming thin film interconnection systems
JPS6019608B2 (ja) * 1978-10-03 1985-05-17 シャープ株式会社 電極パタ−ン形成方法
US4285780A (en) * 1978-11-02 1981-08-25 Schachter Herbert I Method of making a multi-level circuit board
US4181755A (en) * 1978-11-21 1980-01-01 Rca Corporation Thin film pattern generation by an inverse self-lifting technique
US4275286A (en) * 1978-12-04 1981-06-23 Hughes Aircraft Company Process and mask for ion beam etching of fine patterns
US4202914A (en) * 1978-12-29 1980-05-13 International Business Machines Corporation Method of depositing thin films of small dimensions utilizing silicon nitride lift-off mask
JPS5595340A (en) * 1979-01-10 1980-07-19 Chiyou Lsi Gijutsu Kenkyu Kumiai Preparation of semiconductor device
US4272561A (en) * 1979-05-29 1981-06-09 International Business Machines Corporation Hybrid process for SBD metallurgies
JPS55163860A (en) * 1979-06-06 1980-12-20 Toshiba Corp Manufacture of semiconductor device
US4371423A (en) * 1979-09-04 1983-02-01 Vlsi Technology Research Association Method of manufacturing semiconductor device utilizing a lift-off technique
JPS5710926A (en) * 1980-06-25 1982-01-20 Toshiba Corp Manufacture of semiconductor device
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process
US4407859A (en) * 1980-10-17 1983-10-04 Rockwell International Corporation Planar bubble memory circuit fabrication
US4339305A (en) * 1981-02-05 1982-07-13 Rockwell International Corporation Planar circuit fabrication by plating and liftoff
EP0057738B1 (de) * 1981-02-07 1986-10-15 Ibm Deutschland Gmbh Verfahren zum Herstellen und Füllen von Löchern in einer auf einem Substrat aufliegenden Schicht
US4517616A (en) * 1982-04-12 1985-05-14 Memorex Corporation Thin film magnetic recording transducer having embedded pole piece design
US4391849A (en) * 1982-04-12 1983-07-05 Memorex Corporation Metal oxide patterns with planar surface
JPS58187260A (ja) * 1982-04-26 1983-11-01 Mitsubishi Electric Corp アルミニウム金属への半田被着法
US4446194A (en) * 1982-06-21 1984-05-01 Motorola, Inc. Dual layer passivation
US4461672A (en) * 1982-11-18 1984-07-24 Texas Instruments, Inc. Process for etching tapered vias in silicon dioxide
US4415606A (en) * 1983-01-10 1983-11-15 Ncr Corporation Method of reworking upper metal in multilayer metal integrated circuits
GB8316477D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
GB2141582B (en) * 1983-06-16 1986-10-29 Plessey Co Plc A method of producing a layered structure
US4451326A (en) * 1983-09-07 1984-05-29 Advanced Micro Devices, Inc. Method for interconnecting metallic layers
US4597177A (en) * 1984-01-03 1986-07-01 International Business Machines Corporation Fabricating contacts for flexible module carriers
WO1985004518A1 (en) * 1984-03-22 1985-10-10 Mostek Corporation Integrated circuits with contact pads in a standard array
US4627151A (en) * 1984-03-22 1986-12-09 Thomson Components-Mostek Corporation Automatic assembly of integrated circuits
US4548903A (en) * 1984-03-30 1985-10-22 The United States Of America As Represented By The Secretary Of The Air Force Method to reveal microstructures in single phase alloys
US4640738A (en) * 1984-06-22 1987-02-03 International Business Machines Corporation Semiconductor contact protection
JPS6276600A (ja) * 1985-09-29 1987-04-08 株式会社　アサヒ化学研究所 基板に導電回路を形成する方法
US4695853A (en) * 1986-12-12 1987-09-22 Hewlett-Packard Company Thin film vertical resistor devices for a thermal ink jet printhead and methods of manufacture
US5162191A (en) * 1988-01-05 1992-11-10 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
US5488394A (en) * 1988-01-05 1996-01-30 Max Levy Autograph, Inc. Print head and method of making same
US4897676A (en) * 1988-01-05 1990-01-30 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
US4961259A (en) * 1989-06-16 1990-10-09 Hughes Aircraft Company Method of forming an interconnection by an excimer laser
US4991285A (en) * 1989-11-17 1991-02-12 Rockwell International Corporation Method of fabricating multi-layer board
JP2881963B2 (ja) * 1990-05-25 1999-04-12 ソニー株式会社 配線基板及びその製造方法
US5726498A (en) * 1995-05-26 1998-03-10 International Business Machines Corporation Wire shape conferring reduced crosstalk and formation methods
US5891804A (en) * 1996-04-18 1999-04-06 Texas Instruments Incorporated Process for conductors with selective deposition
TW480636B (en) * 1996-12-04 2002-03-21 Seiko Epson Corp Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment
US6005198A (en) * 1997-10-07 1999-12-21 Dimensional Circuits Corporation Wiring board constructions and methods of making same
US5994211A (en) 1997-11-21 1999-11-30 Lsi Logic Corporation Method and composition for reducing gate oxide damage during RF sputter clean
US6162365A (en) * 1998-03-04 2000-12-19 International Business Machines Corporation Pd etch mask for copper circuitization
US20060252163A1 (en) * 2001-10-19 2006-11-09 Nano-Proprietary, Inc. Peelable photoresist for carbon nanotube cathode
KR20030068733A (ko) * 2002-02-16 2003-08-25 광전자 주식회사 평탄화 구조를 갖는 반도체 소자 및 그 제조방법
US6569763B1 (en) * 2002-04-09 2003-05-27 Northrop Grumman Corporation Method to separate a metal film from an insulating film in a semiconductor device using adhesive tape
CN100380596C (zh) * 2003-04-25 2008-04-09 株式会社半导体能源研究所 液滴排出装置、图案的形成方法及半导体装置的制造方法
CN100533808C (zh) * 2004-01-26 2009-08-26 株式会社半导体能源研究所 显示器件及其制造方法以及电视设备
US7462514B2 (en) 2004-03-03 2008-12-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same, liquid crystal television, and EL television
US7642038B2 (en) * 2004-03-24 2010-01-05 Semiconductor Energy Laboratory Co., Ltd. Method for forming pattern, thin film transistor, display device, method for manufacturing thereof, and television apparatus
US8158517B2 (en) * 2004-06-28 2012-04-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing wiring substrate, thin film transistor, display device and television device
EA029641B1 (ru) * 2015-02-04 2018-04-30 Открытое акционерное общество "ИНТЕГРАЛ"-управляющая компания холдинга "ИНТЕГРАЛ" Металлизация интегральной схемы
CN117542733B (zh) * 2024-01-10 2024-04-26 合肥晶合集成电路股份有限公司 半导体结构的制作方法、电路及芯片

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US3598710A (en) * 1966-04-04 1971-08-10 Ibm Etching method
US3451867A (en) * 1966-05-31 1969-06-24 Gen Electric Processes of epitaxial deposition or diffusion employing a silicon carbide masking layer
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US3597834A (en) * 1968-02-14 1971-08-10 Texas Instruments Inc Method in forming electrically continuous circuit through insulating layer
US3633269A (en) * 1969-06-24 1972-01-11 Telefunken Patent Method of making contact to semiconductor devices
US3714521A (en) * 1971-07-26 1973-01-30 Rca Corp Semiconductor device or monolithic integrated circuit with tungsten interconnections
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US3837907A (en) * 1972-03-22 1974-09-24 Bell Telephone Labor Inc Multiple-level metallization for integrated circuits
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DE2235749C3 (de) * 1972-07-21 1979-09-20 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum Herstellen eines Leitbahnenmusters
US3877051A (en) * 1972-10-18 1975-04-08 Ibm Multilayer insulation integrated circuit structure
US3873361A (en) * 1973-11-29 1975-03-25 Ibm Method of depositing thin film utilizing a lift-off mask

Also Published As

Publication number Publication date
DE2729030C2 (de) 1982-07-01
CA1082370A (en) 1980-07-22
NL7706108A (nl) 1978-01-03
CH614562A5 (xx) 1979-11-30
IT1115667B (it) 1986-02-03
JPS533172A (en) 1978-01-12
FR2357071B1 (xx) 1980-12-19
DE2729030A1 (de) 1978-01-05
BR7704314A (pt) 1978-05-16
US4076575A (en) 1978-02-28
FR2357071A1 (fr) 1978-01-27

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: INTERNATIONAL BUSINESS MACHINES CORP.

Effective date: 19840527