AU2005269896A1 - A method of and apparatus for implementing fast orthogonal transforms of variable size - Google Patents

A method of and apparatus for implementing fast orthogonal transforms of variable size Download PDF

Info

Publication number
AU2005269896A1
AU2005269896A1 AU2005269896A AU2005269896A AU2005269896A1 AU 2005269896 A1 AU2005269896 A1 AU 2005269896A1 AU 2005269896 A AU2005269896 A AU 2005269896A AU 2005269896 A AU2005269896 A AU 2005269896A AU 2005269896 A1 AU2005269896 A1 AU 2005269896A1
Authority
AU
Australia
Prior art keywords
butterfly
unit
reconfigurable
stage
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2005269896A
Other languages
English (en)
Inventor
Gilad Garon
Doron Solomon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASOCS Ltd
Original Assignee
ASOCS Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/071,340 external-priority patent/US7568059B2/en
Application filed by ASOCS Ltd filed Critical ASOCS Ltd
Publication of AU2005269896A1 publication Critical patent/AU2005269896A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Algebra (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Discrete Mathematics (AREA)
  • Complex Calculations (AREA)
AU2005269896A 2004-07-08 2005-07-08 A method of and apparatus for implementing fast orthogonal transforms of variable size Abandoned AU2005269896A1 (en)

Applications Claiming Priority (13)

Application Number Priority Date Filing Date Title
US58638904P 2004-07-08 2004-07-08
US58639104P 2004-07-08 2004-07-08
US58639004P 2004-07-08 2004-07-08
US58635304P 2004-07-08 2004-07-08
US60/586,353 2004-07-08
US60/586,390 2004-07-08
US60/586,389 2004-07-08
US60/586,391 2004-07-08
US60425804P 2004-08-25 2004-08-25
US60/604,258 2004-08-25
US11/071,340 US7568059B2 (en) 2004-07-08 2005-03-03 Low-power reconfigurable architecture for simultaneous implementation of distinct communication standards
US11/071,340 2005-03-03
PCT/US2005/024063 WO2006014528A1 (en) 2004-07-08 2005-07-08 A method of and apparatus for implementing fast orthogonal transforms of variable size

Publications (1)

Publication Number Publication Date
AU2005269896A1 true AU2005269896A1 (en) 2006-02-09

Family

ID=35787416

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2005269896A Abandoned AU2005269896A1 (en) 2004-07-08 2005-07-08 A method of and apparatus for implementing fast orthogonal transforms of variable size

Country Status (6)

Country Link
EP (1) EP1769391A1 (enExample)
JP (1) JP2008506191A (enExample)
KR (1) KR101162649B1 (enExample)
AU (1) AU2005269896A1 (enExample)
CA (1) CA2563450A1 (enExample)
WO (1) WO2006014528A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009110022A1 (ja) * 2008-03-03 2009-09-11 富士通株式会社 無線通信装置
FR2935819B1 (fr) * 2008-09-05 2010-09-10 Commissariat Energie Atomique Dispositif de traitement numerique pour transformee de fourier et filtrage a reponse impulsionnelle finie
CN102737007B (zh) * 2011-04-07 2015-01-28 中兴通讯股份有限公司 一种支持多个数据单元任意置换的方法和装置
JPWO2013042249A1 (ja) * 2011-09-22 2015-03-26 富士通株式会社 高速フーリエ変換回路
WO2013042249A1 (ja) * 2011-09-22 2013-03-28 富士通株式会社 高速フーリエ変換回路
KR101275087B1 (ko) 2011-10-28 2013-06-17 (주)에프씨아이 오에프디엠 수신기
US9525579B2 (en) 2012-07-18 2016-12-20 Nec Corporation FFT circuit
JP6288089B2 (ja) 2013-07-23 2018-03-07 日本電気株式会社 デジタルフィルタ装置、デジタルフィルタ処理方法及びデジタルフィルタプログラムが記憶された記憶媒体
WO2015087495A1 (ja) 2013-12-13 2015-06-18 日本電気株式会社 デジタルフィルタ装置、デジタルフィルタ処理方法及びデジタルフィルタプログラムが記憶された記憶媒体
GB2548908B (en) * 2016-04-01 2019-01-30 Advanced Risc Mach Ltd Complex multiply instruction
KR102155770B1 (ko) * 2018-11-27 2020-09-14 한국항공대학교산학협력단 레이다 응용을 위한 이중 완전 셔플 네트워크 기반 가변 푸리에 변환 장치 및 방법
CN113111300B (zh) * 2020-01-13 2022-06-03 上海大学 具有优化资源消耗的定点fft实现系统
US20230029006A1 (en) * 2020-02-06 2023-01-26 Mitsubishi Electric Corporation Complex multiplication circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU610934B2 (en) * 1987-08-21 1991-05-30 Commonwealth Scientific And Industrial Research Organisation A transform processing circuit
US5293330A (en) * 1991-11-08 1994-03-08 Communications Satellite Corporation Pipeline processor for mixed-size FFTs
WO1997019412A1 (en) * 1995-11-17 1997-05-29 Teracom Svensk Rundradio Improvements in or relating to real-time pipeline fast fourier transform processors
US6003056A (en) * 1997-01-06 1999-12-14 Auslander; Lewis Dimensionless fast fourier transform method and apparatus
JPH11143860A (ja) * 1997-11-07 1999-05-28 Matsushita Electric Ind Co Ltd 直交変換装置
US6061705A (en) * 1998-01-21 2000-05-09 Telefonaktiebolaget Lm Ericsson Power and area efficient fast fourier transform processor
JP2001156644A (ja) * 1999-11-29 2001-06-08 Fujitsu Ltd 直交変換装置
JP3846197B2 (ja) * 2001-01-19 2006-11-15 ソニー株式会社 演算システム
US20030055861A1 (en) * 2001-09-18 2003-03-20 Lai Gary N. Multipler unit in reconfigurable chip
JP4546711B2 (ja) * 2002-10-07 2010-09-15 パナソニック株式会社 通信装置

Also Published As

Publication number Publication date
CA2563450A1 (en) 2006-02-09
KR20070060074A (ko) 2007-06-12
EP1769391A1 (en) 2007-04-04
WO2006014528A1 (en) 2006-02-09
KR101162649B1 (ko) 2012-07-06
JP2008506191A (ja) 2008-02-28

Similar Documents

Publication Publication Date Title
US7870176B2 (en) Method of and apparatus for implementing fast orthogonal transforms of variable size
He et al. A new approach to pipeline FFT processor
Heysters et al. Mapping of DSP algorithms on the MONTIUM architecture
US7849123B2 (en) Pipeline-based reconfigurable mixed-radix FFT processor
WO1997019412A1 (en) Improvements in or relating to real-time pipeline fast fourier transform processors
AU2193599A (en) Pipelined fast fourier transform processor
KR101162649B1 (ko) 가변적 크기의 고속 직교 변환을 구현하기 위한 방법 및장치
US20100122070A1 (en) Combined associative and distributed arithmetics for multiple inner products
JP4163178B2 (ja) 素因数分解アルゴリズムを用いる最適化された離散フーリエ変換方法および装置
CN113568851B (zh) 访问存储器的方法及对应电路
EP1546863B1 (en) Computationally efficient mathematical engine
Joshi FFT architectures: a review
US20100128818A1 (en) Fft processor
EP1429256A2 (en) Apparatus and method for computing an FFT in a programmable processor
EP1076296A2 (en) Data storage for fast fourier transforms
CN100547580C (zh) 用于实现可变大小的快速正交变换的方法和装置
Hassan et al. Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine
US6330580B1 (en) Pipelined fast fourier transform processor
Vergara et al. A 195K FFT/s (256-points) high performance FFT/IFFT processor for OFDM applications
Ward et al. Bit-level systolic array implementation of the Winograd Fourier transform algorithm
Rawski et al. Distributed arithmetic based implementation of Fourier transform targeted at FPGA architectures
CA2451167A1 (en) Pipelined fft processor with memory address interleaving
KR100416641B1 (ko) 프로그래머블 프로세서에서 고속 에프에프티 연산을 위한에프에프티 연산방법 및 그 연산을 실행하기 위한에프에프티 연산회로
Tang et al. A new memory reference reduction method for FFT implementation on DSP
Yamamoto et al. A vector-parallel FFT with a user-specifiable data distribution scheme

Legal Events

Date Code Title Description
MK1 Application lapsed section 142(2)(a) - no request for examination in relevant period