AU2003249230A1 - Method for creating patterns for producing integrated circuits - Google Patents

Method for creating patterns for producing integrated circuits

Info

Publication number
AU2003249230A1
AU2003249230A1 AU2003249230A AU2003249230A AU2003249230A1 AU 2003249230 A1 AU2003249230 A1 AU 2003249230A1 AU 2003249230 A AU2003249230 A AU 2003249230A AU 2003249230 A AU2003249230 A AU 2003249230A AU 2003249230 A1 AU2003249230 A1 AU 2003249230A1
Authority
AU
Australia
Prior art keywords
integrated circuits
producing integrated
creating patterns
patterns
creating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003249230A
Other languages
English (en)
Inventor
Yoshikuni Abe
Aki Fujimura
Robert C. Pack
Louis K. Sheffer
Kenji Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Publication of AU2003249230A1 publication Critical patent/AU2003249230A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/76—Patterning of masks by imaging
    • G03F1/78—Patterning of masks by imaging by charged particle beam [CPB], e.g. electron beam patterning of masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
AU2003249230A 2003-07-14 2003-07-14 Method for creating patterns for producing integrated circuits Abandoned AU2003249230A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2003/021997 WO2005017785A1 (en) 2003-07-14 2003-07-14 Method for creating patterns for producing integrated circuits

Publications (1)

Publication Number Publication Date
AU2003249230A1 true AU2003249230A1 (en) 2005-03-07

Family

ID=34192484

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003249230A Abandoned AU2003249230A1 (en) 2003-07-14 2003-07-14 Method for creating patterns for producing integrated circuits

Country Status (4)

Country Link
EP (1) EP1644855A4 (ja)
JP (1) JP2007521500A (ja)
AU (1) AU2003249230A1 (ja)
WO (1) WO2005017785A1 (ja)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6453452B1 (en) * 1997-12-12 2002-09-17 Numerical Technologies, Inc. Method and apparatus for data hierarchy maintenance in a system for mask description
US6456899B1 (en) * 1999-12-07 2002-09-24 Ut-Battelle, Llc Context-based automated defect classification system using multiple morphological masks
US6444373B1 (en) * 2000-06-16 2002-09-03 Advanced Micro Devices, Inc. Modification of mask layout data to improve mask fidelity
US6353774B1 (en) * 2000-09-22 2002-03-05 Virtek Engineering Sciences Inc. High precision vision guided positioning device
US6526550B1 (en) * 2000-09-29 2003-02-25 General Electric Company Analyzing characteristics of geometries
JP2002196470A (ja) * 2000-12-26 2002-07-12 Hitachi Ltd フォトマスクの製造方法および半導体集積回路装置の製造方法
US6901574B2 (en) * 2001-02-09 2005-05-31 Lacour Patrick J. Data management method for mask writing
US6703167B2 (en) * 2001-04-18 2004-03-09 Lacour Patrick Joseph Prioritizing the application of resolution enhancement techniques
US6560766B2 (en) * 2001-07-26 2003-05-06 Numerical Technologies, Inc. Method and apparatus for analyzing a layout using an instance-based representation
US7302111B2 (en) * 2001-09-12 2007-11-27 Micronic Laser Systems A.B. Graphics engine for high precision lithography
JP2003315973A (ja) * 2002-04-19 2003-11-06 Fujitsu Ltd マスク設計装置、マスク設計方法、プログラムおよび半導体装置製造方法

Also Published As

Publication number Publication date
WO2005017785A1 (en) 2005-02-24
EP1644855A1 (en) 2006-04-12
JP2007521500A (ja) 2007-08-02
EP1644855A4 (en) 2007-08-01

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase