AU2002228779A1 - Cmos inverter circuits utilizing strained silicon surface channel mosfets - Google Patents

Cmos inverter circuits utilizing strained silicon surface channel mosfets

Info

Publication number
AU2002228779A1
AU2002228779A1 AU2002228779A AU2877902A AU2002228779A1 AU 2002228779 A1 AU2002228779 A1 AU 2002228779A1 AU 2002228779 A AU2002228779 A AU 2002228779A AU 2877902 A AU2877902 A AU 2877902A AU 2002228779 A1 AU2002228779 A1 AU 2002228779A1
Authority
AU
Australia
Prior art keywords
cmos inverter
silicon surface
inverter circuits
channel mosfets
strained silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002228779A
Other languages
English (en)
Inventor
Eugene A. Fitzgerald
Nicole Gerrisch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amber Wave Systems Inc
Original Assignee
Amber Wave Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/884,172 external-priority patent/US6649480B2/en
Priority claimed from US09/884,517 external-priority patent/US20020100942A1/en
Application filed by Amber Wave Systems Inc filed Critical Amber Wave Systems Inc
Publication of AU2002228779A1 publication Critical patent/AU2002228779A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
AU2002228779A 2000-12-04 2001-12-04 Cmos inverter circuits utilizing strained silicon surface channel mosfets Abandoned AU2002228779A1 (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US25098500P 2000-12-04 2000-12-04
US60/250,985 2000-12-04
US09/884,172 2001-06-19
US09/884,517 2001-06-19
US09/884,172 US6649480B2 (en) 2000-12-04 2001-06-19 Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US09/884,517 US20020100942A1 (en) 2000-12-04 2001-06-19 CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
PCT/US2001/046322 WO2002047168A2 (fr) 2000-12-04 2001-12-04 Circuits inverseurs cmos utilisant des mosfets a canaux de surface en silicium contraint

Publications (1)

Publication Number Publication Date
AU2002228779A1 true AU2002228779A1 (en) 2002-06-18

Family

ID=27400407

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002228779A Abandoned AU2002228779A1 (en) 2000-12-04 2001-12-04 Cmos inverter circuits utilizing strained silicon surface channel mosfets

Country Status (5)

Country Link
US (1) US20020125471A1 (fr)
EP (1) EP1399970A2 (fr)
JP (1) JP2004523103A (fr)
AU (1) AU2002228779A1 (fr)
WO (1) WO2002047168A2 (fr)

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US6602613B1 (en) 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6969875B2 (en) 2000-05-26 2005-11-29 Amberwave Systems Corporation Buried channel strained silicon FET using a supply layer created through ion implantation
AU2001283138A1 (en) * 2000-08-07 2002-02-18 Amberwave Systems Corporation Gate technology for strained surface channel and strained buried channel mosfet devices
EP1309989B1 (fr) 2000-08-16 2007-01-10 Massachusetts Institute Of Technology Procede de production d'articles semiconducteurs par croissance epitaxiale graduelle
US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6900103B2 (en) * 2001-03-02 2005-05-31 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6723661B2 (en) * 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
AU2002322105A1 (en) * 2001-06-14 2003-01-02 Amberware Systems Corporation Method of selective removal of sige alloys
US7301180B2 (en) 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
EP1399974A1 (fr) * 2001-06-21 2004-03-24 Massachusetts Institute Of Technology Mosfets a couches semi-conductrices contraintes
WO2003015142A2 (fr) 2001-08-06 2003-02-20 Massachusetts Institute Of Technology Formation de couches planes soumises a des contraintes
US7138649B2 (en) * 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
EP1428262A2 (fr) 2001-09-21 2004-06-16 Amberwave Systems Corporation Structures semi-conductrices utilisant des couches de materiaux sollicites a gradients d'impurete definis et procedes de fabrication correspondants
US6933518B2 (en) 2001-09-24 2005-08-23 Amberwave Systems Corporation RF circuits including transistors having strained material layers
JP2005516389A (ja) 2002-01-23 2005-06-02 スピネカ セミコンダクター， インコーポレイテッド 歪み半導体基板を用いてショットキまたはショットキのような接触を形成するソースおよび／またはドレインを有する電界効果トランジスタ
US6974737B2 (en) * 2002-05-16 2005-12-13 Spinnaker Semiconductor, Inc. Schottky barrier CMOS fabrication method
WO2003105204A2 (fr) 2002-06-07 2003-12-18 Amberwave Systems Corporation Dispositifs a semi-conducteur comprenant des couches contraintes en tension a deux canaux
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6900521B2 (en) * 2002-06-10 2005-05-31 Micron Technology, Inc. Vertical transistors and output prediction logic circuits containing same
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
JP5144002B2 (ja) 2002-08-23 2013-02-13 台湾積體電路製造股▲ふん▼有限公司 減少した転位パイルアップを有する半導体ヘテロ構造および関連した方法
US6882010B2 (en) * 2002-10-03 2005-04-19 Micron Technology, Inc. High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters
JP2004172389A (ja) * 2002-11-20 2004-06-17 Renesas Technology Corp 半導体装置およびその製造方法
US6903384B2 (en) * 2003-01-15 2005-06-07 Sharp Laboratories Of America, Inc. System and method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications
US6828628B2 (en) * 2003-03-05 2004-12-07 Agere Systems, Inc. Diffused MOS devices with strained silicon portions and methods for forming same
JP5288707B2 (ja) * 2003-03-12 2013-09-11 エーエスエム アメリカ インコーポレイテッド シリコンゲルマニウムの、平坦化及び欠陥密度を減少させる方法
US6900502B2 (en) * 2003-04-03 2005-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel on insulator device
US6882025B2 (en) * 2003-04-25 2005-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Strained-channel transistor and methods of manufacture
US6867433B2 (en) 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US7662701B2 (en) 2003-05-21 2010-02-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US7501329B2 (en) * 2003-05-21 2009-03-10 Micron Technology, Inc. Wafer gettering using relaxed silicon germanium epitaxial proximity layers
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US7164182B2 (en) * 2003-07-07 2007-01-16 Micron Technology, Inc. Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
US20050012087A1 (en) * 2003-07-15 2005-01-20 Yi-Ming Sheu Self-aligned MOSFET having an oxide region below the channel
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US6940705B2 (en) * 2003-07-25 2005-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor with enhanced performance and method of manufacture
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US5155571A (en) * 1990-08-06 1992-10-13 The Regents Of The University Of California Complementary field effect transistors having strained superlattice structure
EP0838858B1 (fr) * 1996-09-27 2002-05-15 Infineon Technologies AG Circuit intégré CMOS et son procéde de fabrication
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WO1999053539A1 (fr) * 1998-04-10 1999-10-21 Massachusetts Institute Of Technology Systeme de couche d'arret d'attaque chimique au silicium et au germanium
JP3403076B2 (ja) * 1998-06-30 2003-05-06 株式会社東芝 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JP2004523103A (ja) 2004-07-29
WO2002047168A2 (fr) 2002-06-13
WO2002047168A3 (fr) 2003-12-31
US20020125471A1 (en) 2002-09-12
EP1399970A2 (fr) 2004-03-24

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