AU2001274700A1 - Timing control means for automatic compensation of timing uncertainties - Google Patents

Timing control means for automatic compensation of timing uncertainties

Info

Publication number
AU2001274700A1
AU2001274700A1 AU2001274700A AU7470001A AU2001274700A1 AU 2001274700 A1 AU2001274700 A1 AU 2001274700A1 AU 2001274700 A AU2001274700 A AU 2001274700A AU 7470001 A AU7470001 A AU 7470001A AU 2001274700 A1 AU2001274700 A1 AU 2001274700A1
Authority
AU
Australia
Prior art keywords
timing
control means
automatic compensation
uncertainties
timing control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001274700A
Other languages
English (en)
Inventor
Igor Anatolievich Abrosimov
Alexander Roger Deas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/RU2000/000188 external-priority patent/WO2001091131A1/en
Application filed by Individual filed Critical Individual
Publication of AU2001274700A1 publication Critical patent/AU2001274700A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
AU2001274700A 2000-05-22 2001-05-22 Timing control means for automatic compensation of timing uncertainties Abandoned AU2001274700A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
AU68811/00 2000-05-22
PCT/RU2000/000188 WO2001091131A1 (en) 2000-05-22 2000-05-22 Timing control means for automatic compensation of timing uncertainties
US22811500P 2000-08-28 2000-08-28
US60/228,115 2000-08-28
PCT/RU2001/000202 WO2001090864A2 (en) 2000-05-22 2001-05-22 Timing control means for automatic compensation of timing uncertainties

Publications (1)

Publication Number Publication Date
AU2001274700A1 true AU2001274700A1 (en) 2001-12-03

Family

ID=26653587

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001274700A Abandoned AU2001274700A1 (en) 2000-05-22 2001-05-22 Timing control means for automatic compensation of timing uncertainties

Country Status (5)

Country Link
US (1) US6834255B2 (ja)
EP (1) EP1360569A2 (ja)
JP (1) JP2004501554A (ja)
AU (1) AU2001274700A1 (ja)
WO (1) WO2001090864A2 (ja)

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JP4118536B2 (ja) * 2001-07-03 2008-07-16 株式会社東芝 クロック遅延設定方法
US7231306B1 (en) * 2002-04-30 2007-06-12 Rambus Inc. Method and apparatus for calibrating static timing offsets across multiple outputs
US7072355B2 (en) * 2003-08-21 2006-07-04 Rambus, Inc. Periodic interface calibration for high speed communication
US7050919B1 (en) * 2003-11-19 2006-05-23 Analog Devices, Inc. Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock period
US8422568B2 (en) 2004-01-28 2013-04-16 Rambus Inc. Communication channel calibration for drift conditions
US7400670B2 (en) 2004-01-28 2008-07-15 Rambus, Inc. Periodic calibration for communication channels by drift tracking
US7095789B2 (en) 2004-01-28 2006-08-22 Rambus, Inc. Communication channel calibration for drift conditions
US7158536B2 (en) 2004-01-28 2007-01-02 Rambus Inc. Adaptive-allocation of I/O bandwidth using a configurable interconnect topology
US6961862B2 (en) 2004-03-17 2005-11-01 Rambus, Inc. Drift tracking feedback for communication channels
US7061285B2 (en) * 2004-04-15 2006-06-13 Woods Paul R Clock doubler
US7024326B2 (en) * 2004-04-30 2006-04-04 Infineon Technologies Ag Method of optimizing the timing between signals
US7978754B2 (en) * 2004-05-28 2011-07-12 Rambus Inc. Communication channel calibration with nonvolatile parameter store for recovery
US7516029B2 (en) 2004-06-09 2009-04-07 Rambus, Inc. Communication channel calibration using feedback
US7535958B2 (en) * 2004-06-14 2009-05-19 Rambus, Inc. Hybrid wired and wireless chip-to-chip communications
GB2415555B (en) * 2004-06-26 2008-05-28 Plus Design Ltd Signalling method
US7551646B1 (en) * 2004-09-10 2009-06-23 Xilinx, Inc. Data alignment and deskewing module
US7489739B2 (en) 2004-09-17 2009-02-10 Rambus, Inc. Method and apparatus for data recovery
US7457589B2 (en) * 2004-11-30 2008-11-25 Infineon Technologies Ag Circuit and method for transmitting a signal
US7262637B2 (en) * 2005-03-22 2007-08-28 Micron Technology, Inc. Output buffer and method having a supply voltage insensitive slew rate
US7647028B2 (en) * 2005-04-06 2010-01-12 Skyworks Solutions, Inc. Internal calibration system for a radio frequency (RF) transmitter
US7212045B2 (en) * 2005-07-25 2007-05-01 Logan Technology Corp. Double frequency signal generator
US7233170B2 (en) * 2005-08-25 2007-06-19 International Business Machines Corporation Programmable driver delay
JP2007208774A (ja) * 2006-02-03 2007-08-16 Yokogawa Electric Corp 位相制御回路
US7536579B2 (en) * 2006-08-03 2009-05-19 Avalon Microelectronics, Inc. Skew-correcting apparatus using iterative approach
US7760836B2 (en) * 2006-08-03 2010-07-20 Avalon Microelectronics, Inc. Skew-correcting apparatus using external communications element
US7546494B2 (en) * 2006-08-03 2009-06-09 Avalon Microelectronics Inc. Skew-correcting apparatus using dual loopback
US20080253491A1 (en) * 2007-04-13 2008-10-16 Georgia Tech Research Corporation Method and Apparatus for Reducing Jitter in Multi-Gigahertz Systems
JP5258343B2 (ja) * 2008-03-27 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置及び半導体集積回路
US7831856B1 (en) 2008-04-03 2010-11-09 Lattice Semiconductor Corporation Detection of timing errors in programmable logic devices
WO2010100730A1 (ja) 2009-03-04 2010-09-10 富士通株式会社 データ転送装置、データ送信装置、データ受信装置および制御方法
US8582706B2 (en) * 2009-10-29 2013-11-12 National Instruments Corporation Training a data path for parallel data transfer
US8276014B2 (en) * 2010-02-12 2012-09-25 The Regents Of The University Of Michigan Stalling synchronisation circuits in response to a late data signal
WO2011161828A1 (ja) * 2010-06-25 2011-12-29 富士通株式会社 データ伝送システム、データ伝送方法および送信装置
US8774228B2 (en) 2011-06-10 2014-07-08 International Business Machines Corporation Timing recovery method and apparatus for an input/output bus with link redundancy
US9474492B2 (en) 2012-05-22 2016-10-25 Siemens Medical Solutions Usa, Inc. Adaptive ECG trigger signal jitter detection and compensation for imaging systems
CN104052710B (zh) * 2014-06-24 2017-07-14 华为技术有限公司 数字发射机的调制电路、数字发射机和信号调制方法
US9985618B2 (en) * 2015-12-23 2018-05-29 Qualcomm Incorporated Digital duty cycle correction for frequency multiplier
US10551869B2 (en) * 2016-02-26 2020-02-04 Arizona Board Of Regents On Behalf Of Arizona State University Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs
US11217298B2 (en) * 2020-03-12 2022-01-04 Micron Technology, Inc. Delay-locked loop clock sharing

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US4929850A (en) * 1987-09-17 1990-05-29 Texas Instruments Incorporated Metastable resistant flip-flop
US5249132A (en) * 1990-10-31 1993-09-28 Tektronix, Inc. Digital pulse generator
US5767715A (en) * 1995-09-29 1998-06-16 Siemens Medical Systems, Inc. Method and apparatus for generating timing pulses accurately skewed relative to clock
JP2967713B2 (ja) * 1995-12-26 1999-10-25 日本電気株式会社 クロックパルス位相制御回路
US6002282A (en) * 1996-12-16 1999-12-14 Xilinx, Inc. Feedback apparatus for adjusting clock delay
US6043694A (en) * 1998-06-24 2000-03-28 Siemens Aktiengesellschaft Lock arrangement for a calibrated DLL in DDR SDRAM applications

Also Published As

Publication number Publication date
US6834255B2 (en) 2004-12-21
US20010056332A1 (en) 2001-12-27
WO2001090864A2 (en) 2001-11-29
EP1360569A2 (en) 2003-11-12
JP2004501554A (ja) 2004-01-15
WO2001090864A3 (en) 2003-01-03

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