AU2001258577A1 - Switched-based time synchronization protocol for a numa system - Google Patents

Switched-based time synchronization protocol for a numa system

Info

Publication number
AU2001258577A1
AU2001258577A1 AU2001258577A AU5857701A AU2001258577A1 AU 2001258577 A1 AU2001258577 A1 AU 2001258577A1 AU 2001258577 A AU2001258577 A AU 2001258577A AU 5857701 A AU5857701 A AU 5857701A AU 2001258577 A1 AU2001258577 A1 AU 2001258577A1
Authority
AU
Australia
Prior art keywords
time base
nodes
base register
packet
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001258577A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of AU2001258577A1 publication Critical patent/AU2001258577A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/26—Flow control; Congestion control using explicit feedback to the source, e.g. choke packets
    • H04L47/266—Stopping or restarting the source, e.g. X-on or X-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
  • Mobile Radio Communication Systems (AREA)
AU2001258577A 2000-05-25 2001-05-18 Switched-based time synchronization protocol for a numa system Abandoned AU2001258577A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/578,740 2000-05-25
US09/578,740 US6687756B1 (en) 2000-05-25 2000-05-25 Switched-based time synchronization protocol for a NUMA system
PCT/GB2001/002242 WO2001090910A2 (en) 2000-05-25 2001-05-18 Switched-based time synchronization protocol for a numa system

Publications (1)

Publication Number Publication Date
AU2001258577A1 true AU2001258577A1 (en) 2001-12-03

Family

ID=24314109

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001258577A Abandoned AU2001258577A1 (en) 2000-05-25 2001-05-18 Switched-based time synchronization protocol for a numa system

Country Status (11)

Country Link
US (1) US6687756B1 (zh)
EP (1) EP1292897B1 (zh)
KR (1) KR100483262B1 (zh)
CN (1) CN1199121C (zh)
AT (1) ATE291758T1 (zh)
AU (1) AU2001258577A1 (zh)
BR (1) BR0102131A (zh)
CA (1) CA2409205A1 (zh)
DE (1) DE60109612D1 (zh)
TW (1) TWI220200B (zh)
WO (1) WO2001090910A2 (zh)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10147422A1 (de) * 2001-09-26 2003-04-24 Siemens Ag Kommunikationssystem und Verfahren zur Synchronisation eines Kommunikationszyklus
CN1328555C (zh) * 2002-02-22 2007-07-25 塔尔科技有限公司 微型制冷的方法与装置
US7111195B2 (en) * 2002-02-25 2006-09-19 General Electric Company Method and system for external clock to obtain multiple synchronized redundant computers
DE10241429B4 (de) * 2002-09-06 2007-10-25 Siemens Ag Verfahren zur Synchronisation von Netzwerkknoten eines Teilnetzwerks
US20050254506A1 (en) * 2004-05-11 2005-11-17 Derek Edward Davout Gladding Apparatus and method for transporting data over a ring structure
US20060161647A1 (en) * 2004-12-22 2006-07-20 Waldemar Wojtkiewicz Method and apparatus providing measurement of packet latency in a processor
US7395448B2 (en) * 2006-07-26 2008-07-01 International Business Machines Corporation Directly obtaining by application programs information usable in determining clock accuracy
CN102799212B (zh) * 2012-07-16 2015-05-27 中船重工（武汉）凌久电子有限责任公司 用于多核多处理器并行系统的全局时钟系统及其使用方法
US9483325B2 (en) * 2012-09-28 2016-11-01 Hewlett Packard Enterprise Development Lp Synchronizing timestamp counters
EP2929434B1 (en) * 2012-12-06 2019-01-16 Coherent Logix Incorporated Processing system with synchronization instruction
KR102020358B1 (ko) * 2013-03-14 2019-11-05 삼성전자 주식회사 단말 및 그 단말에서 애플리케이션 동기화 방법
US9237093B2 (en) * 2013-03-14 2016-01-12 Silicon Graphics International Corp. Bandwidth on-demand adaptive routing
US9256534B2 (en) 2014-01-06 2016-02-09 International Business Machines Corporation Data shuffling in a non-uniform memory access device
US9274835B2 (en) 2014-01-06 2016-03-01 International Business Machines Corporation Data shuffling in a non-uniform memory access device
US9568944B2 (en) * 2014-11-14 2017-02-14 Cavium, Inc. Distributed timer subsystem across multiple devices
US10944694B2 (en) 2016-12-06 2021-03-09 Hewlett Packard Enterprise Development Lp Predictive arbitration circuit
US10452573B2 (en) 2016-12-06 2019-10-22 Hewlett Packard Enterprise Development Lp Scripted arbitration circuit
US10237198B2 (en) 2016-12-06 2019-03-19 Hewlett Packard Enterprise Development Lp Shared-credit arbitration circuit
US10721185B2 (en) 2016-12-06 2020-07-21 Hewlett Packard Enterprise Development Lp Age-based arbitration circuit
US10693811B2 (en) 2018-09-28 2020-06-23 Hewlett Packard Enterprise Development Lp Age class based arbitration

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4591977A (en) * 1983-03-23 1986-05-27 The United States Of America As Represented By The Secretary Of The Air Force Plurality of processors where access to the common memory requires only a single clock interval
US5250943A (en) 1991-03-29 1993-10-05 International Business Machines Corporation GVT-NET--A Global Virtual Time Calculation Apparatus for Multi-Stage Networks
US5390216A (en) * 1991-11-02 1995-02-14 Robert Bosch Gmbh Synchronization method for a mobile radiotelephone
US5600822A (en) * 1994-04-05 1997-02-04 International Business Machines Corporation Resource allocation synchronization in a parallel processing system
JP2908739B2 (ja) * 1994-12-16 1999-06-21 インターナショナル・ビジネス・マシーンズ・コーポレイション 多重プロセッサ・システムにおけるｃｐｕのモニタリング・システム及び方法
WO1996031033A2 (en) * 1995-03-29 1996-10-03 Philips Electronics N.V. System for providing a predetermined timing relation between inputting and outputting of data; transmitter and receiver for such a system
US5822381A (en) * 1995-05-05 1998-10-13 Silicon Graphics, Inc. Distributed global clock system
US5905869A (en) 1996-09-27 1999-05-18 Hewlett-Packard, Co. Time of century counter synchronization using a SCI interconnect
US5896524A (en) * 1997-02-06 1999-04-20 Digital Equipment Corporation Off-line clock synchronization for multiprocessor event traces
DE69833933T2 (de) 1998-07-09 2006-09-28 Bull S.A. Mehrprozessorsystem mit synchronisierter Systemzeit

Also Published As

Publication number Publication date
DE60109612D1 (de) 2005-04-28
ATE291758T1 (de) 2005-04-15
EP1292897B1 (en) 2005-03-23
CA2409205A1 (en) 2001-11-29
WO2001090910A3 (en) 2003-01-09
CN1326150A (zh) 2001-12-12
KR20030005332A (ko) 2003-01-17
WO2001090910A2 (en) 2001-11-29
TWI220200B (en) 2004-08-11
BR0102131A (pt) 2001-12-26
CN1199121C (zh) 2005-04-27
US6687756B1 (en) 2004-02-03
EP1292897A2 (en) 2003-03-19
KR100483262B1 (ko) 2005-04-15

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