AU2001257491A1 - Staggered bitline strapping of a non-volatile memory cell - Google Patents

Staggered bitline strapping of a non-volatile memory cell

Info

Publication number
AU2001257491A1
AU2001257491A1 AU2001257491A AU5749101A AU2001257491A1 AU 2001257491 A1 AU2001257491 A1 AU 2001257491A1 AU 2001257491 A AU2001257491 A AU 2001257491A AU 5749101 A AU5749101 A AU 5749101A AU 2001257491 A1 AU2001257491 A1 AU 2001257491A1
Authority
AU
Australia
Prior art keywords
staggered
memory cell
volatile memory
bitline
strapping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001257491A
Other languages
English (en)
Inventor
Pau-Ling Chen
Richard M. Fastow
Shane Charles Hollmer
Mark W. Randolph
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2001257491A1 publication Critical patent/AU2001257491A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
AU2001257491A 2000-05-16 2001-05-01 Staggered bitline strapping of a non-volatile memory cell Abandoned AU2001257491A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US20446700P 2000-05-16 2000-05-16
US60204467 2000-05-16
US09/718,771 US6593606B1 (en) 2000-05-16 2000-11-22 Staggered bitline strapping of a non-volatile memory cell
US09718771 2000-11-22
PCT/US2001/014134 WO2001088987A2 (fr) 2000-05-16 2001-05-01 Cablage etage de la ligne de bits d'une cellule de memoire non volatile

Publications (1)

Publication Number Publication Date
AU2001257491A1 true AU2001257491A1 (en) 2001-11-26

Family

ID=26899501

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001257491A Abandoned AU2001257491A1 (en) 2000-05-16 2001-05-01 Staggered bitline strapping of a non-volatile memory cell

Country Status (3)

Country Link
US (1) US6593606B1 (fr)
AU (1) AU2001257491A1 (fr)
WO (1) WO2001088987A2 (fr)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6917544B2 (en) * 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
JP4817617B2 (ja) * 2004-06-14 2011-11-16 株式会社東芝 不揮発性半導体記憶装置
US20060036803A1 (en) * 2004-08-16 2006-02-16 Mori Edan Non-volatile memory device controlled by a micro-controller
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7153755B2 (en) * 2005-01-26 2006-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Process to improve programming of memory cells
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US7786512B2 (en) 2005-07-18 2010-08-31 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
JP2012064898A (ja) * 2010-09-17 2012-03-29 Toshiba Corp 露光方法及び半導体装置の製造方法
US9786719B2 (en) * 2012-03-07 2017-10-10 Micron Technology, Inc. Method for base contact layout, such as for memory
KR20160001152A (ko) 2014-06-26 2016-01-06 삼성전자주식회사 비휘발성 메모리 소자

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168334A (en) 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
JPH03166762A (ja) * 1989-11-27 1991-07-18 Sony Corp 半導体メモリ
US6410990B2 (en) * 1997-12-12 2002-06-25 Intel Corporation Integrated circuit device having C4 and wire bond connections
JP3225916B2 (ja) 1998-03-16 2001-11-05 日本電気株式会社 不揮発性半導体記憶装置とその製造方法
US6215148B1 (en) 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6034882A (en) * 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6366501B1 (en) * 2000-02-29 2002-04-02 Advanced Micro Devices, Inc. Selective erasure of a non-volatile memory cell of a flash memory device

Also Published As

Publication number Publication date
US6593606B1 (en) 2003-07-15
WO2001088987A3 (fr) 2002-04-11
WO2001088987A2 (fr) 2001-11-22

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